Memory/macro internal clock insertion delay

Hi ,

My memories/macros .lib has internal clock insertion delay defined on CLK pin of memory/macro with propert max/min_clock_tree_path . we have concern over register to memory paths where capture path is memory.

If i consider one register to memory path . Tool is balacing well register with memory with including internal memory latency with 100 ps skew . But if we consider till CLK pin of memory the skew between register and memory CLK pin(in this case no internal latency) becomes around 500 ps which is creating a very large violation during report_timing .

I believe tool s doing right thing only reporting is issue . Please correct if i am wrong . If i am correct , please help on how to consider internal macro latency as well during report timing .

Thanks in advance ,

Argha

Very unlikely that reporting is the only issue. Make sure the paths are timed correctly during OPT, depending on the info you put on the .lib and on the tool configuration, some data paths are ignored by the tool.