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Microcontroller uart transmission working in debug mode but not in program mode

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BoopathiS

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Hi,
I'm interfacing three STM 32 bit controller using internal UART communication. Consider one as master and other two are slave(Slave 1 and Slave 2) . In debug mode, UART transmission and reception happening between both master and slaves. When going to program mode, From Master to Slave 1 data is transmitting, but from slave 1 to master there is no transmission. clock is connected to external crystal.

Same Master connected to another slave 2(has same slave circuit and program and clock frequency) through another uart port of master controller, with this slave 2 uart communication is working fine in both debug and program mode.

Verified both slaves:
supply voltage, Clock frequency, Reset pin state, data rate looking fine.
Components in both slave circuit, Connections of both slace circuits looking fine

Myself, Difficult to identify root cause. Can anyone help me to identify this issue.
 

Some drawings would be helpful.

What is the config for the UARTs on every node?
 

UART communication is not really "master-slave" - each end of the channel can send whenever it likes.
Do the devices that you refer to 'Slave 1' and 'Slave 2' share wire for both of their 'Tx' signals to the 'Master's Rx line? If so then this is a very bad design without something else in the circuit. Basically a UART will keep its Tx line in the 'idle' state when not in use. The 'idle' state is typically 'high' (but you can define it to be 'low' if you like - you can control these things in your design). If you don't 'tri-state' the Tx lines when they are connected together, then when one 'slave' tries to send, the 'idle' state of the other 'slave' will interfere with the signal and you will not communicate properly.
Susan
 

UART communication is not really "master-slave" - each end of the channel can send whenever it likes.
Do the devices that you refer to 'Slave 1' and 'Slave 2' share wire for both of their 'Tx' signals to the 'Master's Rx line? If so then this is a very bad design without something else in the circuit. Basically a UART will keep its Tx line in the 'idle' state when not in use. The 'idle' state is typically 'high' (but you can define it to be 'low' if you like - you can control these things in your design). If you don't 'tri-state' the Tx lines when they are connected together, then when one 'slave' tries to send, the 'idle' state of the other 'slave' will interfere with the signal and you will not communicate properly.
Susan

Do the devices that you refer to 'Slave 1' and 'Slave 2' share wire for both of their 'Tx' signals to the 'Master's Rx line?

No, Both slave connected to Master controller in different UART port.

Default Tx line is high level.
 

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