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  1. #1
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    SDC constraints for asynchronous reset

    Hello fellow engineers!

    For my master thesis I am working on a digital correlator circuit. Sadly I didn't learn much about asic design during my studies (only FPGA).

    For the regular circuit operation I was able to write SDC constraints and the post-synthesis simulation with annotated SDF files works as it should.
    I have one particular problem with the asynchronous reset of my RTL design: the synthesis tool adds in an inverter to change from my designed active high reset to the active low reset of the standard cells I use. (I am using LFoundry 150nm process).
    When I had a look at the schematic of the syntesized design, I saw that it only uses a 0.5*drivestrenght inverter. It is a small design so, it only has to drive about 50 FFs, so I simulated the situation in virtuoso (using the 0.5 inverter and a load capacitance of 50*4fF which I got from the Databook) and as I expected the reset would take several nanoseconds to become active. Because of that I added the following to my SDC constraints:

    create_clock -name RESEThigh -period 2 -waveform {0.0 0.70} [get_ports iRESET]
    set_clock_groups -asynchronous -group RESEThigh
    set_clock_transition 0.1 [all_clocks]

    But this doesnt change the syntesis. It still only uses the 0.5d INV.

    Please tell me what I am doing wrong and how to do it right! If you need HDL source files or the whole SDC constraints, please tell me I can give those to you, but due to NDA I cannot give you the finished synthesized design.


    As a second question: How to proceed after place and route (i am using innovus)? Do I just extract the netlist and post PnR SDF and simulate, and if the simmulation is correct the chip is finished? I am asking because my department normaly works exclusively on analog circuits in virtuoso and they normaly do a post layout simulation of the whole chip before giving it to the manufacturer. Is there a way to get my whole design done in innovus into virtuoso and do full transient analysis of it? (The design is not that big, only about 600 std cells, so simulation time shoudlnt that much of a concern). Also what is the right way to merge a mixed signal circuit? my digital part will work of input signals generated by an analog circuit done by a coleague. It would be nice to inport the innovus design to virtuoso so I have the netlist as schematic and the layout also in there. I have tried importing the GDS stream into virtuoso but it only gives me the layout, but I may have done somethign wrong!

    Thank you very much!


    Alex

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  2. #2
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    Re: SDC constraints for asynchronous reset

    1) do not create a clock. reset is not a clock, period. If the reset is async, then you have to make sure it stays async. by default the synthesis tool will assume it is async, so don't put any input delay on it. a syncronizer would fix your problem here, just put a flop connected to the primary input reset. all other flops in the circuit receive the reset post sync.

    2) for real world digital asics there is no way you can do spice simulation, even gate level simulation is impossible these days. for your design you can, but so what? what you do is robust RTL simulation and trust your timing tool did a good job. that is enough for an academic project.

    3) for integrating you have to decide if it is analog on top or digital on top. no ASIC is really 100% analog these days, so I suggest using digital on top. you get the GDS and L;EF from your colleague and input that to Innovus. Your RTL code must also instantiate the analog component. that is all there is to it.
    Really, I am not Sam.



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  3. #3
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    Re: SDC constraints for asynchronous reset

    Adding a clock to a reset signal even gives the design more issues.
    Please remove it.
    To improve one's brain, the doors are needed over the keys.



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