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[SOLVED] How to Simulate Designs with L=50um

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rmanalo

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Hello Everyone,

I'm trying to simulate the Design from the paper in [1] using HSPICE. The attached are the sizes and schematic of the design.

Sizes.PNGschematic.PNG

In HSPICE the max limit for L is 20um but the design uses 50um. How do I simulate this in HSPICE?

[1] L. Magnelli, et. al., "A 2.6 nW, 0.45 V Temperature Compensated Subthreshold CMOS Voltage Reference," IEEE J. Solid-State Circuits, vol. 46, no. 2, pp.465-474, Feb. 2011.

Best Regards,
rmanalo
 

Connect three MOSFETs of L=50um/3=16.7um in series.

thank you for the reply, correct me if I'm wrong but wouldn't that increase the minimum supply voltage? (I'm thinking connecting three MOSFETs in series would mean having three times the drain-to-source voltage) Additionally all the transistors operate in subthreshold region. I'm not sure about the operation of composite transistors in this region.
 

I'm thinking connecting three MOSFETs in series would mean having three times the drain-to-source voltage
Draw the layout of the 3 series transistor, you will see it is equivalent with one longer device, total Vds will be the same.
Additionally all the transistors operate in subthreshold region. I'm not sure about the operation of composite transistors in this region.
Not all of the series devices will operate in the same region, bottom devices will be in triode region, but the whole transistor will have very similar electrical properties as one long device.
 
You might check where this limit is imposed, there may
be checkboxes (GUI) or flag-variables (SPICE) that will
defeat the error checking. You could also"take the
models private" and edit whatever is the problem -
difference between L=20 and L=50 is probably benign,
and could be sanity-checked in simulation.
 
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