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12th June 2018, 12:40 #1
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Build an Adder using VHDL
My project is 16 bits ALU using VHDL
I am requested to build an adder but not using builtin function, I have to use my own functions and library
How can I start up with codes

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12th June 2018, 12:48 #2
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Re: Build an Adder using VHDL
Hi,
start with the theory.
* are the input values signed or unsigned?
* how does a 1+1 bit adder work?
* do you need to generate carry flag and satus flags?
* then use a pencil and paper and draw a circuit for your 16 bit adder.
* maybe do some optimizations on your circuit
* write code
* test the code. Usual random values but additionally extreme values to thest the extreme situations. Always first write down the expected results, then do the test.
KlausPlease don´t contact me via PM, because there is no time to respond to them. No friend requests. Thank you.
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12th June 2018, 12:53 #3
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Re: Build an Adder using VHDL
can you help me with that if you have a time, please? Actually, I am run of time
Thanks in Advance

12th June 2018, 13:12 #4
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Re: Build an Adder using VHDL
Hi,
not "I", but "we", the forum.
And "help" means: You do the job, and we "help" to find mistakes.
A forum can not replace school and your own will to read documents.
> show what you have done and learned so far.
"time": We will help you to solve the technical problems, but the "time" probelm is yours. Remember: you get the informations for free.
KlausPlease don´t contact me via PM, because there is no time to respond to them. No friend requests. Thank you.

12th June 2018, 13:13 #5
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Re: Build an Adder using VHDL
This code looks like an ALU, and it's your own post:
https://www.edaboard.com/showthread....quotquotquot

12th June 2018, 14:26 #6
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Re: Build an Adder using VHDL
You can find some hints in the Altera Advanced Synthesis Cookbook https://www.altera.com/content/dam/a...x_cookbook.pdf

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12th June 2018, 20:42 #7
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Re: Build an Adder using VHDL
yes it is mine, but I want to built an adder

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13th June 2018, 12:47 #8
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Re: Build an Adder using VHDL
Hi,
try to use XOR and AND logic function to buil 1bit numbers adder with carry.
So you are trying to add: 0+0, 0+1, 1+0, 1+1
You have two outputs: bit position  after adding
carry bit  after adding
So now think how to use xor and and bool function for this purpose.
If yo have one bit adder with carry  you can build N bit adder to join 1bit adders (with carry) N times.
It is easy
Regards

13th June 2018, 14:24 #9
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Re: Build an Adder using VHDL
Hi B21hasni, that may help you https://www.slideshare.net/zbhavyai/...aluusingvhdl
Best Regards

13th June 2018, 15:22 #10
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Re: Build an Adder using VHDL
How can I start up with codes
Study that and then apply that concept in VHDL to model the adder (you have to use the structural coding style rather than behavioral style).
In the text book the eg might be a 4 bits adder example, but the concept can easily be extended to 16 bits. If you are a beginner, just build a 4bits adder first and completely understand how it works.
So write you code, show us what you have done and for sure further help will be available thereafter.FPGA enthusiast!

13th June 2018, 15:48 #11
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Re: Build an Adder using VHDL
According to their other post, this is their graduation project.
FYI, they currently have 3 threads on various aspects of the same project.
At this point I'll assuming they focused on something else (Analog/RF?) and this is the first time they've done a digital design, makes me wonder why they would chose or be directed to work on a graduation project they know nothing about (digital design, VHDL, ALUs, etc). Why aren't they designing a RF power amplifier or an Analog notch filter or something equally more suited to their course work/speciality.

6th July 2018, 13:42 #12
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Re: Build an Adder using VHDL
Code:library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity adder is port( a : in std_logic_vector (15 downto 0); b : in std_logic_vector (15 downto 0); s : out std_logic_vector (15 downto 0); cf : out std_logic; ovf : out std_logic ); end adder; architecture adder of adder is begin process (a,b) variable temp: std_logic_vector (16 downto 0); begin temp := ('0'& a) + ('0'& b); s<= temp(15 downto 0); cf<= temp(16); ovf<= temp(15) xor a(15) xor b(15) xor temp (16); end process; end adder;

6th July 2018, 14:51 #13
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Re: Build an Adder using VHDL
Ovf is useless, as you have a cf output that covers the overflow. The Current OVF bit is just confusing and wrong:
x7FFF + x7FFF = cf=0, s=x"FFFE" and OVF = 1
xFFFF + xFFFF = cf = 1, s=x"FFFE" and OVF = 0
What are you trying to detect with the overflow?

6th July 2018, 18:05 #14
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Re: Build an Adder using VHDL
can I say, this design is an adder??

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7th July 2018, 07:05 #15
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7th July 2018, 11:32 #16
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Re: Build an Adder using VHDL
if I remove ovf what do I have to put instead of ovf<= temp(15) xor a(15) xor b(15) xor temp (16);

7th July 2018, 14:45 #17
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Re: Build an Adder using VHDL
just delete it
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