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    Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator ""+"

    when I compile the program below

    Code VHDL - [expand]
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    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
     
    package ALU is
        function addition (A,B: bit_vector) return bit_vector;
        function subtraction (A,B: bit_vector) return bit_vector;
        function multiplication (A,B: bit_vector) return bit_vector;
        function pass_A (A: bit_vector) return bit_vector;
        function Logical_AND (A,B: bit_vector) return bit_vector;
        function Logical_OR (A,B: bit_vector) return bit_vector;
        function shift_R (A: bit_vector) return bit_vector;
        function shift_L (A: bit_vector) return bit_vector;
            
    end ALU;
     
    package body ALU is
        function addition (A,B: bit_vector) return bit_vector is
        variable Y: bit_vector (15 downto 0);
        begin
        Y := A+B;
        return Y;
        end function;
        
        function subtraction (A,B: bit_vector) return bit_vector is
        variable Y: bit_vector (15 downto 0);
        begin
        Y := A-B;
        return Y;
        end function;
        
        function multiplication (A,B: bit_vector) return bit_vector is
        variable Y: bit_vector (15 downto 0);
        begin
        Y := A*B;
        return Y;
        end function;
        
        function pass_A (A: bit_vector) return bit_vector is
        variable Y: bit_vector (15 downto 0);
        begin
        Y := A;
        return Y;
        end function;
     
        function Logical_AND (A,B: bit_vector) return bit_vector is
        variable Y: bit_vector (15 downto 0);
        begin
        Y := A AND B;
        return Y;
        end function;
     
        function Logical_OR (A,B: bit_vector) return bit_vector is
        variable Y: bit_vector (15 downto 0);
        begin
        Y := A OR B;
        return Y;
        end function;
     
        function shift_R (A: bit_vector) return bit_vector is
        variable Y: bit_vector (15 downto 0);
        begin
        Y := '0'& Y(15 downto 1) ;
        return Y;
        end function;
     
     
        function shift_L (A: bit_vector) return bit_vector is
        variable Y: bit_vector (15 downto 0);
        begin
        Y := Y(14 downto 0)&"0";
        return Y;
        end function;
     
    end package body;
    I got that error
    Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator ""+"" -- found 0 possible definitions
    what is the error in that code ???

  2. #2
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    Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator

    There are no definitions for + with the bit_vector type. numeric_std uses std_logic_vector to define +.
    First time I've seen someone using bit types in their code.



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    Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator

    I replaced all bit_vector with st_logic _vector but I got the same error

    your suggestion did not solve the problem



    •   Alt11th June 2018, 14:46

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  4. #4
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    Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator

    If we talk about standard packages in VHDL, there are two camps: IEEE and Synopsys.
    I couldn't find a better reference right now: https://www.slideshare.net/akhailtas...c-presentation
    IEEE is a recommended way.

    Also check here and here.
    I recommend you to switch from bit_logic to std_logic or better signed/unsigned - this depends on what you want to do.

    To make this code to work with bit_logic: "use ieee.numeric_bit.all;" instead of "use ieee.numeric_std.all;"



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    Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator

    thank you for your suggestion but I still got the error



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    Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator

    If you are using Numeric.std, and you've defined your variables as std_logic, unsigned, signed, etc., then you should not be getting an error. Can you post your revised code?



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    Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator

    not being a VHDL expert,... doesn't the unconstrained width for the inputs require an unconstrained variable instead of variable Y: bit_vector (15 downto 0);?

    Seems to me the variable Y is defining the input (and output) bit widths, which I don't think flies with VHDL.



  8. #8
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    Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator

    If you are using VHDL 2008, then unsigned arithmatic using std_logic_vector and bit_vector is possible via the standard packages:

    ieee.numeric_bit_unsigned.all; -- for bit_vector
    ieee.numeric_std_unsigned.all; -- for std_logic_vector

    If you're using '93 code, then you need to use unsigned/signed type, not std_logic_vector for your types. Unless you use std_logic_unsigned, when "+" is available for std_logic_vector via the non-standard synopsys package (while not an IEEE standard, it is now the same for all vendors - a de-facto standard).

    - - - Updated - - -

    Quote Originally Posted by ads-ee View Post
    not being a VHDL expert,... doesn't the unconstrained width for the inputs require an unconstrained variable instead of variable Y: bit_vector (15 downto 0);?

    Seems to me the variable Y is defining the input (and output) bit widths, which I don't think flies with VHDL.
    It will work just fine - as long as both inputs are also 16 bits.
    Y should be constained to

    std_logic_vector(maximum(a'length, b'length)-1 downto 0);

    These functions also do not cope with overflow.

    Its fairly usual to have unconstrained inputs for functions and procedures. Its even allowable on entities too - this can mean you dont need a generic to size your ports and just let the connection size it for you - you then use attributes internally (this has been valid since '93 )



    •   Alt11th June 2018, 15:54

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  9. #9
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    Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator

    Quote Originally Posted by TrickyDicky View Post
    It will work just fine - as long as both inputs are also 16 bits.
    Figured as much, but didn't think setting the variable width was a good idea as it forces the inputs to only be 16-bits, if that was the case then just make the inputs 16-bits.

    Quote Originally Posted by TrickyDicky View Post
    Y should be constained to

    std_logic_vector(maximum(a'length, b'length)-1 downto 0);
    Thanks Tricky, I figured this was the way to do it, but didn't know the syntax off the top of my head.



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    Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator

    Code VHDL - [expand]
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    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
     
    package ALU is
        function addition (A,B: std_logic_vector) return std_logic_vector;
        function subtraction (A,B: std_logic_vector) return std_logic_vector;
        function multiplication (A,B: std_logic_vector) return std_logic_vector;
        function pass_A (A: std_logic_vector) return std_logic_vector;
        function Logical_AND (A,B: std_logic_vector) return std_logic_vector;
        function Logical_OR (A,B: std_logic_vector) return std_logic_vector;
        function shift_R (A: std_logic_vector) return std_logic_vector;
        function shift_L (A: std_logic_vector) return std_logic_vector;
            
    end ALU;
     
    package body ALU is
        function addition (A,B: std_logic_vector) return std_logic_vector is
        variable Y: std_logic_vector (15 downto 0);
        begin
        Y := A+B;
        return Y;
        end function;
        
        function subtraction (A,B: std_logic_vector) return std_logic_vector is
        variable Y: std_logic_vector (15 downto 0);
        begin
        Y := A-B;
        return Y;
        end function;
        
        function multiplication (A,B: std_logic_vector) return std_logic_vector is
        variable Y: std_logic_vector (15 downto 0);
        begin
        Y := A*B;
        return Y;
        end function;
        
        function pass_A (A: std_logic_vector) return std_logic_vector is
        variable Y: std_logic_vector (15 downto 0);
        begin
        Y := A;
        return Y;
        end function;
     
        function Logical_AND (A,B: std_logic_vector) return std_logic_vector is
        variable Y: std_logic_vector (15 downto 0);
        begin
        Y := A AND B;
        return Y;
        end function;
     
        function Logical_OR (A,B: std_logic_vector) return std_logic_vector is
        variable Y: std_logic_vector (15 downto 0);
        begin
        Y := A OR B;
        return Y;
        end function;
     
        function shift_R (A: std_logic_vector) return std_logic_vector is
        variable Y: std_logic_vector (15 downto 0);
        begin
        Y := '0'& Y(15 downto 1) ;
        return Y;
        end function;
     
     
        function shift_L (A: std_logic_vector) return std_logic_vector is
        variable Y: std_logic_vector (15 downto 0);
        begin
        Y := Y(14 downto 0)&"0";
        return Y;
        end function;
     
    end package body;

    still I have got same error
    Last edited by ads-ee; 11th June 2018 at 22:55. Reason: added tags



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    Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator

    sorry mate, I did not get what did you say



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    Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator

    You can't add std_logic_vectors using numeric_std it's not defined for it. you can recast inside the functions:
    Code VHDL - [expand]
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    function addition (A,B: std_logic_vector) return std_logic_vector is
        variable Y: unsigned (15 downto 0);
        begin
        Y := unsigned(A)+unsigned(B);
        return std_logic_vector(Y);
        end function;
    I really think you should just define A, B, & Y using signed or unsigned in the functions or define it for both (overloaded).

    - - - Updated - - -

    Or as Tricky mentioned:
    Code VHDL - [expand]
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    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std_unsigned.all; -- note this is a new package that handles std_logic_vector as numbers
     
    package ALU is
        function addition (A,B: std_logic_vector) return std_logic_vector;
            
    end ALU;
     
    package body ALU is
        function addition (A,B: std_logic_vector) return std_logic_vector is
        variable Y: std_logic_vector (15 downto 0);
        begin
        Y := A+B;
        return Y;
        end function;
        
    end package body;
    must be compiled with 2008 enabled.



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    Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator

    I am using Quartus Prime Lite Edition 15.1.0.185 software. Is it Okey?



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    Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator

    I am using Quartus Prime Lite Edition 15.1.0.185 software. Is it Okey?
    It does supported the quoted VHDL 2008 libraries.



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    Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator

    Quote Originally Posted by FvM View Post
    It does supported the quoted VHDL 2008 libraries.
    I think that while Quartus 15 does have some VHDL 2008 support, the new libraries have to be added manually, and be the '93 compatible ones.


    1 members found this post helpful.

    •   Alt12th June 2018, 14:37

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  16. #16
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    Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator

    Quote Originally Posted by TrickyDicky View Post
    I think that while Quartus 15 does have some VHDL 2008 support, the new libraries have to be added manually, and be the '93 compatible ones.
    Given the OP's track record and the lack of progress, I think the first suggestion I made in #12 should be what they use. If they do that it should compile, unless that Quartus 15 lacks support for even that much of the newer VHDL standards. I'm too lazy to check what VHDL language versions Quartus 15 supports.

    If that is the case why are they insisting on using numeric_std, they should be using std_logic_unsigned as that was the defacto standard for +/-/* back in the "old" days.



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    Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator

    I think that while Quartus 15 does have some VHDL 2008 support, the new libraries have to be added manually, and be the '93 compatible ones.
    Right, I was mislead by the fact that the libraries are in the quartus ieee/2008 directory, but that apparently means nothing. Needless to say that I have absolutely no use for this stuff anyway.

    Given that ieee.numeric_std_unsigned is just an ieee compatible replacement for the old synopsys ieee.std_logic_unsigned library, you can either use the legacy library or switch to regular numeric_std data types, as everybody suggested.



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    Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator

    There is also an option to include only ieee.std_logic_unsigned."+" (or the numeric_std_unsigned version). This can provide some convenience while not redefining operator "=". In VHDL, comparing vectors of different lengths gives a nice warning. But with numeric_std_unsigned the unsigned interpretations are compared.



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