+ Post New Thread
Results 1 to 18 of 18

11th June 2018, 12:36 #1
 Join Date
 Jun 2018
 Posts
 30
 Helped
 0 / 0
 Points
 166
 Level
 2
Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator ""+"
when I compile the program below
Code VHDL  [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package ALU is function addition (A,B: bit_vector) return bit_vector; function subtraction (A,B: bit_vector) return bit_vector; function multiplication (A,B: bit_vector) return bit_vector; function pass_A (A: bit_vector) return bit_vector; function Logical_AND (A,B: bit_vector) return bit_vector; function Logical_OR (A,B: bit_vector) return bit_vector; function shift_R (A: bit_vector) return bit_vector; function shift_L (A: bit_vector) return bit_vector; end ALU; package body ALU is function addition (A,B: bit_vector) return bit_vector is variable Y: bit_vector (15 downto 0); begin Y := A+B; return Y; end function; function subtraction (A,B: bit_vector) return bit_vector is variable Y: bit_vector (15 downto 0); begin Y := AB; return Y; end function; function multiplication (A,B: bit_vector) return bit_vector is variable Y: bit_vector (15 downto 0); begin Y := A*B; return Y; end function; function pass_A (A: bit_vector) return bit_vector is variable Y: bit_vector (15 downto 0); begin Y := A; return Y; end function; function Logical_AND (A,B: bit_vector) return bit_vector is variable Y: bit_vector (15 downto 0); begin Y := A AND B; return Y; end function; function Logical_OR (A,B: bit_vector) return bit_vector is variable Y: bit_vector (15 downto 0); begin Y := A OR B; return Y; end function; function shift_R (A: bit_vector) return bit_vector is variable Y: bit_vector (15 downto 0); begin Y := '0'& Y(15 downto 1) ; return Y; end function; function shift_L (A: bit_vector) return bit_vector is variable Y: bit_vector (15 downto 0); begin Y := Y(14 downto 0)&"0"; return Y; end function; end package body;
Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator ""+""  found 0 possible definitions

11th June 2018, 14:32 #2
 Join Date
 Sep 2013
 Location
 USA
 Posts
 6,819
 Helped
 1621 / 1621
 Points
 29,529
 Level
 41
Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator
There are no definitions for + with the bit_vector type. numeric_std uses std_logic_vector to define +.
First time I've seen someone using bit types in their code.

Advertisment

11th June 2018, 14:46 #3
 Join Date
 Jun 2018
 Posts
 30
 Helped
 0 / 0
 Points
 166
 Level
 2
Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator
I replaced all bit_vector with st_logic _vector but I got the same error
your suggestion did not solve the problem

11th June 2018, 14:55 #4
 Join Date
 Apr 2018
 Location
 Gdańsk, Poland
 Posts
 90
 Helped
 19 / 19
 Points
 598
 Level
 5
 Blog Entries
 3
Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator
If we talk about standard packages in VHDL, there are two camps: IEEE and Synopsys.
I couldn't find a better reference right now: https://www.slideshare.net/akhailtas...cpresentation
IEEE is a recommended way.
Also check here and here.
I recommend you to switch from bit_logic to std_logic or better signed/unsigned  this depends on what you want to do.
To make this code to work with bit_logic: "use ieee.numeric_bit.all;" instead of "use ieee.numeric_std.all;"

11th June 2018, 15:15 #5
 Join Date
 Jun 2018
 Posts
 30
 Helped
 0 / 0
 Points
 166
 Level
 2
Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator
thank you for your suggestion but I still got the error

11th June 2018, 15:24 #6
 Join Date
 Mar 2005
 Location
 California, USA
 Posts
 4,230
 Helped
 936 / 936
 Points
 22,107
 Level
 36
Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator
If you are using Numeric.std, and you've defined your variables as std_logic, unsigned, signed, etc., then you should not be getting an error. Can you post your revised code?

11th June 2018, 15:44 #7
 Join Date
 Sep 2013
 Location
 USA
 Posts
 6,819
 Helped
 1621 / 1621
 Points
 29,529
 Level
 41
Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator
not being a VHDL expert,... doesn't the unconstrained width for the inputs require an unconstrained variable instead of variable Y: bit_vector (15 downto 0);?
Seems to me the variable Y is defining the input (and output) bit widths, which I don't think flies with VHDL.

11th June 2018, 15:54 #8
 Join Date
 Jun 2010
 Posts
 6,717
 Helped
 1961 / 1961
 Points
 36,811
 Level
 46
Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator
If you are using VHDL 2008, then unsigned arithmatic using std_logic_vector and bit_vector is possible via the standard packages:
ieee.numeric_bit_unsigned.all;  for bit_vector
ieee.numeric_std_unsigned.all;  for std_logic_vector
If you're using '93 code, then you need to use unsigned/signed type, not std_logic_vector for your types. Unless you use std_logic_unsigned, when "+" is available for std_logic_vector via the nonstandard synopsys package (while not an IEEE standard, it is now the same for all vendors  a defacto standard).
   Updated   
It will work just fine  as long as both inputs are also 16 bits.
Y should be constained to
std_logic_vector(maximum(a'length, b'length)1 downto 0);
These functions also do not cope with overflow.
Its fairly usual to have unconstrained inputs for functions and procedures. Its even allowable on entities too  this can mean you dont need a generic to size your ports and just let the connection size it for you  you then use attributes internally (this has been valid since '93 )

Advertisment

11th June 2018, 16:00 #9
 Join Date
 Sep 2013
 Location
 USA
 Posts
 6,819
 Helped
 1621 / 1621
 Points
 29,529
 Level
 41
Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator
Figured as much, but didn't think setting the variable width was a good idea as it forces the inputs to only be 16bits, if that was the case then just make the inputs 16bits.
Thanks Tricky, I figured this was the way to do it, but didn't know the syntax off the top of my head.

11th June 2018, 22:32 #10
 Join Date
 Jun 2018
 Posts
 30
 Helped
 0 / 0
 Points
 166
 Level
 2
Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator
Code VHDL  [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package ALU is function addition (A,B: std_logic_vector) return std_logic_vector; function subtraction (A,B: std_logic_vector) return std_logic_vector; function multiplication (A,B: std_logic_vector) return std_logic_vector; function pass_A (A: std_logic_vector) return std_logic_vector; function Logical_AND (A,B: std_logic_vector) return std_logic_vector; function Logical_OR (A,B: std_logic_vector) return std_logic_vector; function shift_R (A: std_logic_vector) return std_logic_vector; function shift_L (A: std_logic_vector) return std_logic_vector; end ALU; package body ALU is function addition (A,B: std_logic_vector) return std_logic_vector is variable Y: std_logic_vector (15 downto 0); begin Y := A+B; return Y; end function; function subtraction (A,B: std_logic_vector) return std_logic_vector is variable Y: std_logic_vector (15 downto 0); begin Y := AB; return Y; end function; function multiplication (A,B: std_logic_vector) return std_logic_vector is variable Y: std_logic_vector (15 downto 0); begin Y := A*B; return Y; end function; function pass_A (A: std_logic_vector) return std_logic_vector is variable Y: std_logic_vector (15 downto 0); begin Y := A; return Y; end function; function Logical_AND (A,B: std_logic_vector) return std_logic_vector is variable Y: std_logic_vector (15 downto 0); begin Y := A AND B; return Y; end function; function Logical_OR (A,B: std_logic_vector) return std_logic_vector is variable Y: std_logic_vector (15 downto 0); begin Y := A OR B; return Y; end function; function shift_R (A: std_logic_vector) return std_logic_vector is variable Y: std_logic_vector (15 downto 0); begin Y := '0'& Y(15 downto 1) ; return Y; end function; function shift_L (A: std_logic_vector) return std_logic_vector is variable Y: std_logic_vector (15 downto 0); begin Y := Y(14 downto 0)&"0"; return Y; end function; end package body;
still I have got same errorLast edited by adsee; 11th June 2018 at 22:55. Reason: added tags

11th June 2018, 22:39 #11
 Join Date
 Jun 2018
 Posts
 30
 Helped
 0 / 0
 Points
 166
 Level
 2
Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator
sorry mate, I did not get what did you say

11th June 2018, 23:23 #12
 Join Date
 Sep 2013
 Location
 USA
 Posts
 6,819
 Helped
 1621 / 1621
 Points
 29,529
 Level
 41
Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator
You can't add std_logic_vectors using numeric_std it's not defined for it. you can recast inside the functions:
Code VHDL  [expand] 1 2 3 4 5 6
function addition (A,B: std_logic_vector) return std_logic_vector is variable Y: unsigned (15 downto 0); begin Y := unsigned(A)+unsigned(B); return std_logic_vector(Y); end function;
   Updated   
Or as Tricky mentioned:
Code VHDL  [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std_unsigned.all;  note this is a new package that handles std_logic_vector as numbers package ALU is function addition (A,B: std_logic_vector) return std_logic_vector; end ALU; package body ALU is function addition (A,B: std_logic_vector) return std_logic_vector is variable Y: std_logic_vector (15 downto 0); begin Y := A+B; return Y; end function; end package body;

Advertisment

12th June 2018, 12:14 #13
 Join Date
 Jun 2018
 Posts
 30
 Helped
 0 / 0
 Points
 166
 Level
 2
Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator
I am using Quartus Prime Lite Edition 15.1.0.185 software. Is it Okey?

12th June 2018, 14:04 #14
 Join Date
 Jan 2008
 Location
 Bochum, Germany
 Posts
 43,338
 Helped
 13177 / 13177
 Points
 249,046
 Level
 100
Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator
I am using Quartus Prime Lite Edition 15.1.0.185 software. Is it Okey?

12th June 2018, 14:37 #15
 Join Date
 Jun 2010
 Posts
 6,717
 Helped
 1961 / 1961
 Points
 36,811
 Level
 46

12th June 2018, 15:53 #16
 Join Date
 Sep 2013
 Location
 USA
 Posts
 6,819
 Helped
 1621 / 1621
 Points
 29,529
 Level
 41
Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator
Given the OP's track record and the lack of progress, I think the first suggestion I made in #12 should be what they use. If they do that it should compile, unless that Quartus 15 lacks support for even that much of the newer VHDL standards. I'm too lazy to check what VHDL language versions Quartus 15 supports.
If that is the case why are they insisting on using numeric_std, they should be using std_logic_unsigned as that was the defacto standard for +//* back in the "old" days.

12th June 2018, 18:48 #17
 Join Date
 Jan 2008
 Location
 Bochum, Germany
 Posts
 43,338
 Helped
 13177 / 13177
 Points
 249,046
 Level
 100
Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator
I think that while Quartus 15 does have some VHDL 2008 support, the new libraries have to be added manually, and be the '93 compatible ones.
Given that ieee.numeric_std_unsigned is just an ieee compatible replacement for the old synopsys ieee.std_logic_unsigned library, you can either use the legacy library or switch to regular numeric_std data types, as everybody suggested.

13th June 2018, 03:41 #18
 Join Date
 Feb 2015
 Posts
 928
 Helped
 267 / 267
 Points
 5,621
 Level
 17
Re: Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator
There is also an option to include only ieee.std_logic_unsigned."+" (or the numeric_std_unsigned version). This can provide some convenience while not redefining operator "=". In VHDL, comparing vectors of different lengths gives a nice warning. But with numeric_std_unsigned the unsigned interpretations are compared.
+ Post New Thread
Please login