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There are pros and cons. Possibly use NMOS since it might give you somewhat smaller area. Beware of leakage and noise and consider high-voltage (thick-oxide) devices instead of thin-oxide even though they will be larger.
I have used both, sometimes both at once, my primary
interest is what I can hide the bodies under (which bus
is local) and what the specific function wants decoupled
to/from. If you have a strong preference for the B/S/D
to be attached to power planes and the G to the point
of interest, the DC bias imposed by the return connection
and the p.o.i. will indicate what species of FET will be
properly biased there.
Attaching gate to power nets is often either a specific
no-no in ERCs, or just a way to get bit later on when
you're running antenna rules checks. So this may end
up forcing your hand.
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