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    async fifo - almost full/empty

    1. Could you please give me verilog code for generating almost full/empty for async fifo?

    2. Do async fifos typically use almost full/empty instead of full/empty for write/read?

    •   Alt10th June 2018, 08:24

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    Re: async fifo - almost full/empty

    Hi,

    A forum is not meant that someone provides code ...

    You should provide the code and we will help to debug it.

    Additionally you didn't give any informations where exactly you see the problem.

    Klaus
    Please don´t contact me via PM, because there is no time to respond to them. No friend requests. Thank you.



    •   Alt10th June 2018, 11:33

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    Re: async fifo - almost full/empty

    Quote Originally Posted by KlausST View Post
    Hi,

    A forum is not meant that someone provides code ...

    You should provide the code and we will help to debug it.

    Additionally you didn't give any informations where exactly you see the problem.

    Klaus
    1. Compare the counters with some margin for 'almost' calculations and the msb for full/empty. Does this look ok?

    assign almost_empty = (wr_cnt[n-1] - rd_cnt[n-1] < margin) & (wr_cnt[n] & rd_cnt[n]);
    assign almost_full = (rd_cnt[n-1] - wr_cnt[n-1] < margin) & (wr_cnt[n] != rd_cnt[n]);

    2. what do we use almost full/empty indication for async fifo?
    Last edited by stanford; 10th June 2018 at 21:47.



    •   Alt10th June 2018, 21:39

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    Re: async fifo - almost full/empty

    Hi,

    Lucky you, you may decide it on your own, unless you have other informations.

    You may also ask the person who gave you this job.


    Klaus
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    Re: async fifo - almost full/empty

    Do async fifos typically use almost full/empty instead of full/empty for write/read?
    Yes.
    what do we use almost full/empty indication for async fifo?
    Required for flow control applications with delayed response. Think about it, you'll surely understand the purpose. If not, just take it as a requirement that needs to be implemented.



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