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    async fifo - almost full/empty

    1. Could you please give me verilog code for generating almost full/empty for async fifo?

    2. Do async fifos typically use almost full/empty instead of full/empty for write/read?

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    Re: async fifo - almost full/empty

    Hi,

    A forum is not meant that someone provides code ...

    You should provide the code and we will help to debug it.

    Additionally you didn't give any informations where exactly you see the problem.

    Klaus
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    Re: async fifo - almost full/empty

    Quote Originally Posted by KlausST View Post
    Hi,

    A forum is not meant that someone provides code ...

    You should provide the code and we will help to debug it.

    Additionally you didn't give any informations where exactly you see the problem.

    Klaus
    1. Compare the counters with some margin for 'almost' calculations and the msb for full/empty. Does this look ok?

    assign almost_empty = (wr_cnt[n-1] - rd_cnt[n-1] < margin) & (wr_cnt[n] & rd_cnt[n]);
    assign almost_full = (rd_cnt[n-1] - wr_cnt[n-1] < margin) & (wr_cnt[n] != rd_cnt[n]);

    2. what do we use almost full/empty indication for async fifo?
    Last edited by stanford; 10th June 2018 at 21:47.



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    Re: async fifo - almost full/empty

    Hi,

    Lucky you, you may decide it on your own, unless you have other informations.

    You may also ask the person who gave you this job.


    Klaus
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    Re: async fifo - almost full/empty

    Do async fifos typically use almost full/empty instead of full/empty for write/read?
    Yes.
    what do we use almost full/empty indication for async fifo?
    Required for flow control applications with delayed response. Think about it, you'll surely understand the purpose. If not, just take it as a requirement that needs to be implemented.



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    Re: async fifo - almost full/empty

    Quote Originally Posted by FvM View Post
    Yes.

    Required for flow control applications with delayed response. Think about it, you'll surely understand the purpose. If not, just take it as a requirement that needs to be implemented.
    Then how do you make sure you read out everything in the FIFO, if you stop reading when it's almost empty?

    could you give pseudo code to help understand?



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    Re: async fifo - almost full/empty

    Hi,

    Then how do you make sure you read out everything in the FIFO, if you stop reading when it's almost empty?
    When there is an "almost empty" signal, this doesn't necessarily mean that there is no "empty" signal.

    But some applications don't need to know the true "empty state". Like a FIFO for a data stream.
    In a CD player, for example, there is a FIFO.
    The outgoing data rate of this FIFO is quartz stable.. 44100Hz. But the incoming datarate depends on CD spinning speed.
    Thus the "almost empty" signal might be used to speed up the motor, while the "almost full" signal might be used to slow down the motor.

    Klaus
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