Implementing a computer vision algorithm on a FPGA

Hi hardware people,

I'm new to FPGA's and I want to implement a maximum flow solver on a FPGA which is faster than the equivalent written in C. How do I go about starting this project?

The C source can be found here: https://riot.ieor.berkeley.edu/Applications/Pseudoflow/maxflow.html

Thanks in advance,

Rob

synths said:

How do I go about starting this project?

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I think you should start from learning HDL like Verilog or VHDL. Or try using tools like Vivado HLS or Matlab HDL Coder.

Hello,

what is come into my mind is "Vivado HLS" (which means: High Level Synthesis). Why - because there is implementation of this algorithm in C language. With "Vivado HLS" you can try to convert C code into one of HDL languages (Verilog or VHDL). But it is difficult task - you have to be familiar with one of these languages. Another option is to implement Soft-CPU (like Microblaze - Xilinx or NIOSII - Altera) and then port C code to one of these Soft-CPU.

If you are newbie to PLDs (FPGA) it is next to impossible to accomplish such complicated task. You have to make a system of acquisition images from camera (or feed FPGA with images using for example JTAG interface).

Maybe it is worth to take into consideration such technologies as "CUDA" or "Open-CL" (calculation acceleration with GPU) it is much easier to convert given algorithm to them comparing to FPGA.

Regards.

Vivado HLS came to mind for me as well (I use Vivado, though for straight berilog design). They’ve invested substantially in “higher level” design which allows c code and drag and drop of many necessary internal interfaces.

Learning Verilog would be a huge effort but with the higher level interfaces you have a chance of success without needing to dive too deep.

The GPU path seems like another generally good idea though I know nothing about it.

Thank you for your input!
I will look into Vivaldi HLS, Cuda and OpenCL.

As an alternative to learning Verilog, approximately how much do you estimate contracting a pro to develop it would run me?

synths said:

Thank you for your input!
I will look into Vivaldi HLS, Cuda and OpenCL.

As an alternative to learning Verilog, approximately how much do you estimate contracting a pro to develop it would run me?

Click to expand...

Hello,

at starting point you better do research and check if this algorithm has a implementation in "Open-CL" (Open-CL can be used either on GPU or FPGA).
There is a chance that CUDA/Open-CL implementation of this algorithm is available.

Regards

Take a look at the Xilinx SDSoC which uses Vivado HLS for Zynq devices.
To use it you don't need to know any HDL languages.
You need to select what a function you want to port to FPGA. The software translates it to a block with an AXI interface
This is possible only for the SDSoC platforms, which are already available on the market (check the list on the software site). You can also define your own platform for SDSoC, if you have a PCB with a Zynq device.

Node-Locked License cost is $995.

Sounds great?! The devil is always in the details...
You need to know a specific compiler pragmas to port functions properly to the FPGA.
Also it is good to know some HDL language and Zynq architecture to figure out how to fix possible timing issues in the FPGA project.