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  1. #1
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    Why does this current limiter oscillate?

    I'm struggling to figure out why the circuit below oscillate at about 2-300khz. Changing the value of C10 seems to have no effect, neither does adding an output gate resistor, or adding a input resistor to the non-inverting input. The amplitude of the oscillations goes down if I add a resistor from the op-amp output to ground, but even with a 500Ohm resistor the oscillations are still clear. It doesn't oscillate as long as the output resistance is high enough (Vs_TEY to GND), but it starts to oscillate when the output resistance gets somewhere below 100Ohms. I've though of increasing the gain by using a PNP instead, but I would rather find a solution that works well with a fet as a bipolar transistor would need a constant base current thus making it potentially unsuitable for battery powered operations.

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    Re: Why does this current limiter oscillate?

    Hi,

    Please post the datasheets for:
    * Q1
    * U8

    Klaus
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    Re: Why does this current limiter oscillate?

    I can't get the datasheet for Q1 until Thursday, but here is the datasheet for U8: http://www.st.com/content/ccc/resour...DM00108580.pdf



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    Re: Why does this current limiter oscillate?

    Control amplifier has unity gain at high frequency due to n.i. topology, multiplied with FET stage gain it's probably too much.

    Need additional pole or pole/zero for loop gain roll-off.



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    Re: Why does this current limiter oscillate?

    How much is your quescient drain current with 12V supply and a 16V zener load in the drain of the FET? If the current is in the cut-off region it creates low frequency poles.
    And don't use 2 series OPAmp in a feedback system. OPAmps have fix internal poles which you cannot modify with external capacitors to compensate in most of the cases, the open-loop gain of 2 series OPAmps is just too high, has no sense and creates a playground for those poles which were compensated originally inside the package.
    "Try SCE to AUX." /John Aaron/



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    Re: Why does this current limiter oscillate?

    That's a rather strange current-limit circuit.
    What is the purpose of D24?
    The way it's configured it would appear that the current-limit current will flow through D24. Is that desired?
    Is the circuit supposed to do anything besides limit current?

    What is the desired current-limit value?
    Zapper
    Curmudgeon Elektroniker



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    Re: Why does this current limiter oscillate?

    It's not two OPs with open loop gain in series. It's G=200 and G=1 amplifier in series. Can be o.k. with an additional dominant pole.

    There's obviously an output load in parallel to the z-diode, omitted in the schematic.



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    Re: Why does this current limiter oscillate?

    Maybe you are right, but I don't see it's G=200 and G=1. I think it is G=200 and G=~140dB. G=1 for the 1st OPAmp would be true if it has connected as a buffer with a separated feedback loop I think. But it is connected to the 2nd OPAmp's output after G=200. I don't know, maybe I am missing something.

    The parallel load wasn't obvious for me either, but I believe for you, that is logical.
    "Try SCE to AUX." /John Aaron/



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    Re: Why does this current limiter oscillate?

    Because you only need to move the Vgs a few mV around the threshold point to vary the current by 100's of mA the gain in the extant ckt is WAYYY too high...

    you have no damping in the feedback network - just a 100nF cap - thus it always overshoots and oscillates ...



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    Re: Why does this current limiter oscillate?

    To get a stable current control loop, two circuit modification are necessary

    - add a dominant pole, e.g. low-pass between U3.1 and U8A.3
    - add Riso of a few 100 ohms between OP output and MOSFET gate, as required according to OP datasheet with large capacitive load



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    Re: Why does this current limiter oscillate?

    Thanks for the replies. Here is the datasheet for the P-ch: http://www.farnell.com/datasheets/20...445.1520919083

    I apologize for not being clear about the load which is indeed connected to the "Vs_TEY" port. The 16V zener acts as over-voltage protection, no current normally flows through it.

    I'm making this thread not only to make the circuit work, but to understand why it works or doesn't work. According to my understanding, at high frequencies, C10 will make U8 unity gain. But at DC the FET is operated in the linear region so the gain much higher. As Easy peasy pointed out, if the op-amp changes it's output voltage by a few mV it will cause a huge change on it's non-inverting input. I guess from the op-amps perspective it has a gain WAY below 1.

    To get a stable current control loop, two circuit modification are necessary

    - add a dominant pole, e.g. low-pass between U3.1 and U8A.3
    - add Riso of a few 100 ohms between OP output and MOSFET gate, as required according to OP datasheet with large capacitive load
    I can understand adding a series gate resistor to make the load less capacitive, but how will adding a low-pass filter from U3.1 to U8A.3 make a difference? Wouldn't that cause even more phase shift in the feedback path? What should the cut-off frequency of this filter be?

    Is there a better way to design a circuit like this by the way? My thinking is the omit the current sense amplifier in the feedback path and use a bipolar transistor instead of a fet?



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    Re: Why does this current limiter oscillate?

    You should really analyze the circuits loop gain. It has various poles, e.g. IN180 frequency response, TSX712 G=1 closed loop response, Q1 miller capacitance pole. They all act in 100 kHz to 1 MHz range, most likely causing a phase margin far below zero. You need a dominant pole that makes the loop gain fall below unity before the phase margin is eaten up. More complex compensations like lag-lead are also possible but I suggest to start with the most simple thing.

    Is there a better way to design a circuit like this by the way?
    Similar circuits often use a N-channel FET and an inverting error amplifier. In this case the OP gain changes from "1 + lowpass" to just lowpass, allowing a simple compensation of the loop gain.



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    Re: Why does this current limiter oscillate?

    the gain of the op-amp is only <1 at high frequencies, put 1k0 in series with C10 and bump up the other res (R97,R102) by a factor of 10, this will give you low gain at intermediate frequencies, and a phase lift where Z of C10 = 1k0.

    If this is not enough, then further, split C10 into a series combo of 220nF + 220nF and put 10k across one of these, this will add damping ...
    Last edited by Easy peasy; 12th June 2018 at 07:31.



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    Re: Why does this current limiter oscillate?

    Hi,

    For sure you may choose another circuit. A couple of month ago we discussed a "voltage controlled current source" ..if I remember right, then it was a one Opamp solution.

    Some issues I see with your circuit:
    * you generate an opamp input voltage of about 1.7V GND referenced.
    * if I calculated right, then your current is set to about 85mA.
    * then you use a 100mOhms shunt, which gives only 8.5mV. (12V referenced)
    * then you transfer this tiny 8.5mV from 12V referenced to GND referenced...with a gain of 200.

    To ease the design, I recommend
    * don't switch to bjt, because with a mosfet you gain accuracy.
    * make all voltages and the regulation 12V referenced. (No need to jump from 12V referenced to GND referenced)
    * use a higher value shunt. (This additionally generates a local feedback for the Mosfet.
    * omit the current measurement amplifier

    Improvements:
    * use a cheap shunt voltage reference instead of the resistive divider to gain precision (not urgently needed when your 12V is accurate and stable)
    * omit the zener diode. (How can a 16V zener be activated with a 12V supply?)
    * maybe use a (zener) diode to keep the Opamp in regulation state...even when no load is connected. (Faster response when a load is connected)

    Klaus
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    Re: Why does this current limiter oscillate?

    I tried increasing the shunt resistor to 1Ohm, set a reference voltage on the non-inverting input to 12V-91mV and then connecting the shunt resistor directly to the inverting input thus omitting the current sense amplifier. For some reason the 100Ohm+13kOhm voltage divider makes a reference voltage of 12V-650mV which means that current is flowing out of the inverting input. Increasing the 100Ohm resistor to 200Ohm increased the refrence voltage to 12V-1.2V. The op-amp has a common mode input voltage of Vcc-0.1V and a input bias current of 50pA max so I don't understand why it's so reluctant to have a high reference voltage at it's input. Replacing the op-amp made no difference.



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    Re: Why does this current limiter oscillate?

    Hi,

    Maybe
    * your lower resistor is way below 13k ... maybe in the range of 1.7k
    * or something else is drawing current
    * or the positive supply (pin 8) is accidentally not connected to 12V
    * or the OPAMP is defective. (ESD?)

    Klaus

    Mind not to let the unused inputs floating. (of the second OPAMP)
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  17. #17
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    Re: Why does this current limiter oscillate?

    This particular op-amp has a maximum allowable input voltage of vcc-0.2V and gnd+0.2V, it starts doing weird stuff if I exceed these limits. Perhaps I could allow a shunt resistor big enough to get ~0.25V of drop to avoid the current sense amplifier, but that would be unsatisfying. I will increase the shunt to 1Ohm and decrease the current sense amplifier gain to 10 and see how that goes.

    To ease the design, I recommend
    * don't switch to bjt, because with a mosfet you gain accuracy.
    * make all voltages and the regulation 12V referenced. (No need to jump from 12V referenced to GND referenced)
    * use a higher value shunt. (This additionally generates a local feedback for the Mosfet.
    * omit the current measurement amplifier
    How will using a mosfet gain accuracy as opposed to a bjt? As long as the system stays stable it wouldn't matter, right? By using a base resistor of correct value I can drastically reduce the loop gain which is a good thing, right?

    Even if I can get this particular circuit stable, is there a way to 'make sure' circuits like these are stable when designing them, other than choosing the exact same designs as I've made before?



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    Re: Why does this current limiter oscillate?

    Hi,

    If you still have problems with your circuit, then please show the complete schematic and PCB layout.
    In which post I have to look to find what "this particular OPAMP" is?

    vcc-0.2V and gnd+0.2V
    ... these are not typical values.

    it starts doing weird stuff if I exceed these limits.
    .. weird stuff?

    How will using a mosfet gain accuracy as opposed to a bjt?
    The OPAMP regulates shunt voltage. Shunt voltage = shunt_current * R_shunt

    output_current = shunt_current - base_current. (or gate current for a MOSFET)

    Now that the gate current can be considered to be zero (compared to the base current) --> MOSFET circuit is much more accurate.

    By using a base resistor of correct value I can drastically reduce the loop gain which is a good thing, right?
    I usually use local HF feedback at the OPAMP. This makes it stable. Get some ideas here: https://www.edaboard.com/showthread....current-source

    Klaus
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