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  1. #1
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    Help - ATM With VHDL (to store passwords)

    Hello.

    I have a big problem. I have to work on a ATM machine that can store at least 99 data (in this case passwords for 99 different users) and i have no clue on how to do this.

    So, i started by attaching a 4X4 Keyboard to the FPGA (Altera DE2), then i programmed it and made it show the input number on the 7 segment display. However, i have no clue on what to do next, i've been thinking about creating 99 passwords that will be pre-defined, so that would be like making 99 different cases for the 99 passwords that will be 4 digits. But, even if it works, makes no sense. The user should be able to set the password so the machine remembers it. I've been thinking about doing a "master password" that will allow the user to generate one password that will be stored somewhere for the machine to read it later, and of course a reset button.

    Here is the code for the 4x4 keyboard:

    Code VHDL - [expand]
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    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
     
    entity teclado is
    Port ( columnas : in std_logic_vector(3 downto 0);
           ck : in std_logic;
           filas : out std_logic_vector(3 downto 0);
           dato : out std_logic_vector(6 downto 0);
           pulso : out std_logic);
    end teclado;
     
     
    architecture Behavioral of teclado is
    signal cont: std_logic_vector(1 downto 0); 
    signal dec_filas: std_logic_vector(3 downto 0);
    signal dec_dato: std_logic_vector(6 downto 0);
    signal c3, c2, c1, c0: std_logic;
    signal pulsoT: std_logic;
    begin
    Process(ck)
    begin
         if (ck'event and ck='0') then
             cont<=cont+1;
         end if;
    end process;
    Process(ck)
    begin
         if (ck'event and ck='1') then
              if (columnas="1000") then
                   c3<='1';
                   pulsoT <= '1';
              elsif(columnas="0100") then
                   c2<='1';
                   pulsoT <= '1';
              elsif(columnas="0010") then
                   c1<='1';
                   pulsoT <= '1';
              elsif (columnas="0001") then
                   c0<='1';
                   pulsoT <= '1';
              elsif(cont = "11" and(c3='1' or c2='1' or c1='1' or c0='1'))then
                   c0<='0'; c1<='0'; c2<='0'; c3<='0';
              elsif(cont = "11" and c3='0' and c2='0' and c1='0' and c0='0')then
                   pulsoT <= '0';
              end if;
         end if;
    end process;
    process(ck)
    begin
         if(ck'event and ck='0')then
              if (columnas/="0000" and(c0='1' or c1='1' or c2='1' or c3='1')  )        then
                   dato<=dec_dato;
             end if;
         end if;
    end process;
    dec_filas <= "0001" when cont="00" else
             "0010" when cont="01" else
             "0100" when cont="10" else
             "1000" when cont="11" else
             "0000";
    filas<= dec_filas;
    dec_dato <= "0000001" when dec_filas="0100" and columnas="0001"          else --0
             "1001111" when dec_filas="1000" and columnas="1000"          else --1
             "0010010" when dec_filas="0100" and columnas="1000"          else --2
             "0000110" when dec_filas="0010" and columnas="1000"          else --3
             "1001100" when dec_filas="1000" and columnas="0100"          else --4
             "0100100" when dec_filas="0100" and columnas="0100"          else --5 
             "1100000" when dec_filas="0010" and columnas="0100"          else --6
             "0001111" when dec_filas="1000" and columnas="0010"          else --7
             "0000000" when dec_filas="0100" and columnas="0010"          else --8
             "0001100" when dec_filas="0010" and columnas="0010"          else --9
             "0111111" when dec_filas="0001" and columnas="1000"          else --A
             "1011111" when dec_filas="0001" and columnas="0100"          else --B
             "1101111" when dec_filas="0001" and columnas="0010"          else --C
             "1110111" when dec_filas="0001" and columnas="0001"          else --D
             "1111011" when dec_filas="0010" and columnas="0001"          else --#
             "1111101" when dec_filas="1000" and columnas="0001"          else --*
             "0000000";
    pulso<= pulsoT;
    End Behavioral;

    So, the next step would be creating the password mechanism, but i don't know how to do that. Can someone help me? I've asked my teacher and he tells me that i should try reading about sorting mechanisms...well...i did, but i just don't understand how they work and how those mechanisms could help me.

    Thanks for your time.
    Last edited by BradtheRad; 9th June 2018 at 06:14. Reason: Added code formatted window

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  2. #2
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    Re: Help - ATM With VHDL (to store passwords)

    Hi,

    This sounds to be a better job for a microcontroller than for a FPGA.

    If you want to go on with the FPGA
    (I don't know this FPGA, but I assume there is no EEPROM insude)
    Thus I'd connect a serial EEPROM for the usernames and passwords.
    If safety is an issue you have to encrypt the data.

    Klaus
    Please don´t contact me via PM, because there is no time to respond to them. No friend requests. Thank you.



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    Re: Help - ATM With VHDL (to store passwords)

    So, I made a driagram last night, hope you understand.
    Click image for larger version. 

Name:	B00C93A4-2E5E-4EAE-856A-19640F19E835.jpeg 
Views:	10 
Size:	171.9 KB 
ID:	147132
    That’s the program I want to make, right now I’m trying to store the data from the keyboard into a variable. Then I will store 4 different data that will be the 4 digits of the password.



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    Re: Help - ATM With VHDL (to store passwords)

    DE2 is a Cyclone II FPGA eval board, not a FPGA.

    Click image for larger version. 

Name:	de2.PNG 
Views:	4 
Size:	195.1 KB 
ID:	147131


    In has on-board parallel flash, so it could theoretically store passwords, but I guess that's beyond the scope of this exercise problem. It's probably fine to have the passwords stored in FPGA registers or block RAM, preloaded with default content, editable but lost when you shut down the power.

    Similarly, I presume the exercise doesn't involve encryption…

    To organize sequential process flow (e.g. of an "ATM") in hardware logic, you need to build a finite state machine (or multiple hierarchical FSM). Best start to sketch a state diagrams of the intended function. Start with simple parts like the multiple digit password entry.

    - - - Updated - - -

    Although sorting algorithms may be used, they aren't necessary for a basic implementation. No problem to compare an entered password against all stored values without previous sorting. Start to define some parameters minimal and maximal password length, used alphabet, necessary control keys (at least backspace and enter, I guess).

    - - - Updated - - -

    That looks O.K. for the top level state machine. There must be lower level state machines for the keyboard entry.



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    Re: Help - ATM With VHDL (to store passwords)

    Hello,

    maybe it is worth to use Soft-Processor (for Altera De2: NIOS or NIOSII) - it simplifies most task you have to accomplish. And even password encryption in such case is easy (you can use algorithms in C language).

    Regards.



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    Re: Help - ATM With VHDL (to store passwords)

    Quote Originally Posted by FlyingDutch View Post
    Hello,

    maybe it is worth to use Soft-Processor (for Altera De2: NIOS or NIOSII) - it simplifies most task you have to accomplish. And even password encryption in such case is easy (you can use algorithms in C language).

    Regards.
    Could you help me with that? I mean, if you could explain a little bit what you mean. I really have no idea on how to continue with this program, I haven’t slept in 3 days reading and trying to figure out. I’ve been thinking about an array of data where I have 3 columns and 99 lines, each line with User/Password/Money Balance, but I’ve been searching and I don’t find the way to do that. Like, I could do it with 99 separate cases ,but of course that doesn’t make any sense in terms of efficiency and it would take forever to program. I really appreciate your help, and sorry for taking your time.



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    Re: Help - ATM With VHDL (to store passwords)

    maybe it is worth to use Soft-Processor (for Altera De2: NIOS or NIOSII) - it simplifies most task you have to accomplish.
    As far as I understand, this is a HDL exercise, if so, soft processors aren't an option.

    I’ve been thinking about an array of data where I have 3 columns and 99 lines, each line with User/Password/Money Balance, but I’ve been searching and I don’t find the way to do that. Like, I could do it with 99 separate cases ,but of course that doesn’t make any sense in terms of efficiency and it would take forever to program.
    Why 99 cases? The interesting feature of an array is that the rows can be addressed by an index variable, so the code for row access has to be written only once. In terms of hardware implementation, an array can be either a sea of bit registers or real RAM. Without considering special rules, your code will most likely end up with the former, not actually efficient FPGA code, but at least efficient writing.

    - - - Updated - - -

    As a first step, you can define types and global signals and write state machine code for the top level design in post #3.



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