sanjaysharmaiitk
Member level 1
i have designed, a ASIC chip OF UART using verilog code as a input using .
BAUD RATE GENERATOR clock divide by dividing factor.
at post layout simulation on HSPICE (including parasitic capacitance and resistances after PEX analysis by Calibre tool in virtuoso) clock after dividing by 5 result are not accurate some randomly varied .
how can i design a reliable accurate digital clock divider block.
BAUD RATE GENERATOR clock divide by dividing factor.
at post layout simulation on HSPICE (including parasitic capacitance and resistances after PEX analysis by Calibre tool in virtuoso) clock after dividing by 5 result are not accurate some randomly varied .
how can i design a reliable accurate digital clock divider block.