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[moved] 50Mz to 1 kHz clock generator

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sanjaysharmaiitk

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i have designed, a ASIC chip OF UART using verilog code as a input using .
BAUD RATE GENERATOR clock divide by dividing factor.
at post layout simulation on HSPICE (including parasitic capacitance and resistances after PEX analysis by Calibre tool in virtuoso) clock after dividing by 5 result are not accurate some randomly varied .
how can i design a reliable accurate digital clock divider block.
Screenshot-1.png Screenshot-2.png Screenshot-3.png
 

Re: 50Mz to 1 kHz clock generator

Hi,

the diagrams just show the results, but not how you designed your circuit.
Without your circuit the diagrams are about meaningless.
--> Show us your circuit.

You say "divide by 5" but the diagram#2 shows "divide by 11", the diagram #3 shows a "divide by 10".
The variation is wrong for a fixed divider (maybe timing violation), but it may be correct for an NCO.

The gaps of diagram#1 are odd.

Klaus

- - - Updated - - -

Hi,

the usual UART baud rates are 2^n x 9600
Where 9600 = 2^7 x 3 x 5^2

but 50M = 50,000,000 = 2^7 x 5^8

For an integer divider there is the problem that in 9600 there is a "3", but this is missing in 50M
For an integer divider it´s more easy if you work from an 48MHz clock, which is 2^10 x 3 x 5^6 (instead of 50MHz)

Klaus
 
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