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Hardware Utilization Efficiency

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rafimiet

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Given the hardware utilization of a design using FPGA, how can we calculate its Hardware Utilization Efficiency (HUE)?
 

What is this HUE metric of which you speak, I can only find it referenced here: https://ieeexplore.ieee.org/document/5118242/
The way it is talked about here, it is not a factor of hardware utilization, but more about how well the design is pipelined - ie. how many idle cycles compared to active cycles.
This is something that will be design dependent and depend on many factors, and will only be calculated by the user through theory or from experimentation.
 
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