[SOLVED] PCB High Speed Routing: Confusing matching length tolerances specified in ps

Hello to all,
This is my first post.

Becoming from RF world I recently migrated to PCB routing in high speed digital designs, so I take care about signal integrity, crosstalk, impedance matchng, etc, I must route all signals betwenn QDR memory (CY7C2665KV18) and very fast FPGA from microsemi. Regarding "QDR®-II, QDR-II+, DDR-II, and DDR-II+ Design Guide" App Note AN4065 from Cypress https://www.cypress.com/file/38596/download at page 11 says:

All Data, Address and Clock lines must be matched
closely within ±10 ps within each bus type and
between buses. Alternatively, in terms of length, the
matching translates to +/-60 mils using 160 ps per
inch of trace length. Also Clock lines should be kept
away from other signal and Clock lines to a minimum
of 5x the trace width or larger if space allows.

Click to expand...

This memory runs at 550MHz but double rate for both ports lead us to 1 GHz

Ok, the tolerances are specified in picoseconds I tried to determine how much is in terms of length, so first able, let's take 160ps per inch as speed of electromagnetic wave in the medium (PCB dielectrics):

160 ps -> 1 inch -> 25.4 mm
+/-10ps -> +/-0.0625 inch -> +/-1.5875 mm


If I calculate the speed of EM Wave in the medium (I use er= 3.6), v = c/sqrt(3.6) = 158.138e6 m/s, so for 10picoseconds this lead us around 1.58 mm, very close to first calculation. However an experienced routers in high speed digital design says me that this is a very broad tolerance, they use normally around +/-0.2 mm. Taking these remarks as true, I could be wrong in a factor x10,
What's could be wrong in my reasoning ?

Thanks in advance.

The manufacturing tolerances -perhaps-have been taken into account too..Otherwise, the calculation is correct.

+/- 0.2mm sounds inappropriately low. Where do you see the specification?

Hi, FvM +/- 0.2 mm just listened by experienced routers, but I agree with you that sounds very low tolerances. ALl that I just know is if my calculations gives something "normal" in terms of high speed routing tolerances.

Your calculation is what is required by Altera's core, which already meets the requirements for the routing. Tightening the tolerances to the level that the "experienced routers" are requiring seems more like a case of:
"we once had a problem on board X and we fixed the problem by tightening up the routing to +/- 0.2 mm, therefore all boards from now on with DDR memory have to be routed to +/-0.2 mm." This seems more likely as they don't seem to have a good reason behind this requirement.

To put it another way, if you look at if from the perspective of what is the delay between traces for 0.2 mm...
it is 1.26 ps (using the 160ps/in). Well 1.26 ps might make a difference on a differential pair for a 10 Gb serial connection, where even small phase difference can be a problem, but isn't going to do a thing for single ended SSTL lines from a DDR memory as the DLL in the memory and the PLLs in the FPGA aren't capable of single digit ps resolution. Besides that the package pin delays are on the order of 10's of ps, so they should be compensated for in the routing of the traces, which completely blows up the 0.2 mm trace matching requirement.

We had to do "trace matching" (actually should be referred to as path delay matching) to ensure our DDR3 1600 would work, as the combined FPGA/DDR3 package pin delays exceeded the DDR3 controller core compensation range. And yes the DDR3 worked the first time we powered it up with a 10 mil trace matching requirement, the board guy did better and had it within 8 mil.

Agree with the above, why make life hard, getting 0.2mm on all DDR lines is a pain, I have had to do it to +/- 0.25mm for a job, painful, very painful.

That's sounds very rational and the calculations never lie :smile: . With respect to trace matching, I didn't found anything about package pin delays. All that I wanted was a reference or indicative magnitude in order to guide me and ensure that there was no error in application of my criteria because this is my first time routing high speed digital designs.
Thank you very much.