Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

TSMC 65nm Substrate Issues

Status
Not open for further replies.
P

Puppet123

Full Member level 6
Joined
Apr 26, 2017
Messages
356
Helped
22
Reputation
44
Reaction score
21
Trophy points
18
Activity points
3,059
Hello,

I am using TMSC 65nm process and to know how to make substrate contacts for layout in this process.

Do I just make a P+ connection on a PWELL unit cell and the connect this cell liberally on my layout ground plane ?

Any other suggestions, issues or tips ?

Thank you.
 

In my opinion, you just need to do that.

If your circuit has BJT which has more than one VSS connections, for example normal VSS and VSSPS connected to collector. Then pay attention that the substrate is needed to connect with VSSPS instead of VSS.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top