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Binary weighted switch for r-2r DAC

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mburakbaran

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Hi all,

I designed a 12bit DAC based on R-2R topology in a 0.18um CMOS tech. It is 8+4bit segmented. The sizes of the switches are increased in a binary weighted manner as the current drawn from each consecutive higher significant bit is going to be double. So, the switch of the LSB is 1 unit, LSB+1 is 2 unit so for and so forth. The segmented parts switch size is equal to each other (4to15 thermometer decoder, thus 15 of them) two times the last non-segmented switch size and 15 is equal. This way, I was able to minimize the systematic mismatch.

Anyways, here comes my question. How do I lay this out? If I go ahead and try to form something like a common-centroid array, the more the fingers gets away from the center, the more rds it will add to that specific finger, and adding yet another systematic mismatch in terms of "Ron" dont you think? How would you suggest I should proceed? (Please bear in mind that the smallest switch is 1 unit, yet the biggest ones (the unary part) are 256 x unit)

Any help is greatly appreciated. Thanks a lot.
 

Probably you have a voltage reference, not current based R2R DAC, so the Ron of the switches can change from code to code value. This is usually a bigger problem of a 12bit DAC than the layout, however sizes of your devices also matter, but you didn't share.
So, I am not sure that the current through your switches change by this rule what you described. Are you sure that the tap currents of the ladder follow this rule that higher significant bit's tap current is always doubled compared to next lower? I think every tap current depend from every tap currents (ON or OFF) if the reference is a voltage source. Or I couldn't imagine your architecture well, could you post a schematic? Would be better.
How much is your R value? Compared to R how much is maximum Ron? Are you sure that DNL and INL depend more from Ron and parasitics than mismatch of resistors?
And I don't understand your problem, if the Ron of the switches is low enough common centroid is so important? I think if you cannot ensure enough low Ron you should increase R.
 

Hello, attached is a representative drawing I just made, excuse me for the image but am away from my terminal and did not want to lose time.
Let me try and clarify things further. Yes you are right, this is based on a Vref. And the input resistance is code dependent. What I tried to do here via adding a replica of S1 switch (unit switch, smallest one, thus the biggest Ron, which is around 600 ohm if I remember correctly) to the node at the down right of the schematic (where there should normally be directly the ground only) and making it "on" all the time, I am somewhat making sure that dividing into 2 at the every branch of the converter is made sure. E.g. Consider when all the bits are zero, and only b1 is 1, so Vref is fed there, apply superposition, Vref / 8 is seen at the output. If there was no constantly on s1 at the ground branch, I'd have made a systematic mistake in the first place...

So the topology is like this. S1 is unit size, S2 is 2xS1, S3 is 4xS1 etc etc. The value R is set to be around 21k. Although 21k vs 600 ohm (biggest ron) is not that different in order Ron to be neglected, but hopefully thanks to the constantly on S1 at the lower branch before the ground, there is a compensation is happening.
I hope this clarifies what I am trying to do, and why I need the Rons to match (i.e. to make S1,S2,S3 to have Ron, Ron/2, Ron/4 respectively).

I appreciate your assistance...



Probably you have a voltage reference, not current based R2R DAC, so the Ron of the switches can change from code to code value. This is usually a bigger problem of a 12bit DAC than the layout, however sizes of your devices also matter, but you didn't share.
So, I am not sure that the current through your switches change by this rule what you described. Are you sure that the tap currents of the ladder follow this rule that higher significant bit's tap current is always doubled compared to next lower? I think every tap current depend from every tap currents (ON or OFF) if the reference is a voltage source. Or I couldn't imagine your architecture well, could you post a schematic? Would be better.
How much is your R value? Compared to R how much is maximum Ron? Are you sure that DNL and INL depend more from Ron and parasitics than mismatch of resistors?
And I don't understand your problem, if the Ron of the switches is low enough common centroid is so important? I think if you cannot ensure enough low Ron you should increase R.

20180601_233236.jpg
 

In RDACs I have done, I made a "unit cell" consisting of
single finger FETs plus the resistor, parallel 2, 3, 8, 16
for the MSBs and use R2R for the LSBs again with the
FETs in place but fixed "on" biased to the rails. 2R is
2 series (R+FET).
 

Hello. I did not really understand your concept but unfortunately I cannot afford to create such a unit cell as I already laid out the resistor core. Time is of the essence too. I am all ears if you have any other insight about this. Thanks a lot.

In RDACs I have done, I made a "unit cell" consisting of
single finger FETs plus the resistor, parallel 2, 3, 8, 16
for the MSBs and use R2R for the LSBs again with the
FETs in place but fixed "on" biased to the rails. 2R is
2 series (R+FET).
 

Hi,

your OPAMP circuit is wrong.
* Either use a feedback resistor in inverting configuration
* or use it in non inverting configuraton.

In either case I recommend to put a low pass filter into the signal line just to avoid that the OPAMP input stage gets temporarily overdriven by high dU/dt switched input signals.

Klaus
 

So the topology is like this. S1 is unit size, S2 is 2xS1, S3 is 4xS1 etc etc. The value R is set to be around 21k. Although 21k vs 600 ohm (biggest ron) is not that different in order Ron to be neglected, but hopefully thanks to the constantly on S1 at the lower branch before the ground, there is a compensation is happening.
I hope this clarifies what I am trying to do, and why I need the Rons to match (i.e. to make S1,S2,S3 to have Ron, Ron/2, Ron/4 respectively).
You ruined every 2R branch by changing the sizes of the switches from branch 2 branch. It is not the correct way, 2R branches have to be the same as R branches just 2 times bigger.
So what dick_freebird described is a much better solution to improve linearity: build up the R branches from a switch+R, 2R branches from 2 series switch + 2 series R, and you can switch the 2 series switches as on your figure.
At thermometer section probably you did it well, on the figure it is not visible unfortunately, but at R2R what you told is not correct, sorry.
As KlausST mentioned the OPAmp is figured in a meaningless scenario, you probably wanted to draw a buffer. R2R can work with buffer and inverting amplifier too, but the inverting amplifier forces constant voltage by the virtuaal ground to the ladder's output, which reduces the voltage variation on your switches caused by the changing current through them. It also improves linearity, I suggest that.
 

Hi, I was in a hurry, the drawing is incorrect. Normally it is in non-inverting configuration.

Hi,

your OPAMP circuit is wrong.
* Either use a feedback resistor in inverting configuration
* or use it in non inverting configuraton.

In either case I recommend to put a low pass filter into the signal line just to avoid that the OPAMP input stage gets temporarily overdriven by high dU/dt switched input signals.

Klaus

- - - Updated - - -

Hello again. Could you take a look at the drawing I attached now? Can you explain to me why this would be ruining every branch? When you take a look at the impedances from an arbitrary branch and follow that to the output, you must see that at the every next stage it gets divided by 2. I am not saying this is the best way to compensate the switch resistance, considering the area penalty in the end, but I'd like to understand if I am mathematically missing something here... Thanks again for your help.

You ruined every 2R branch by changing the sizes of the switches from branch 2 branch. It is not the correct way, 2R branches have to be the same as R branches just 2 times bigger.
So what dick_freebird described is a much better solution to improve linearity: build up the R branches from a switch+R, 2R branches from 2 series switch + 2 series R, and you can switch the 2 series switches as on your figure.
At thermometer section probably you did it well, on the figure it is not visible unfortunately, but at R2R what you told is not correct, sorry.
As KlausST mentioned the OPAmp is figured in a meaningless scenario, you probably wanted to draw a buffer. R2R can work with buffer and inverting amplifier too, but the inverting amplifier forces constant voltage by the virtuaal ground to the ladder's output, which reduces the voltage variation on your switches caused by the changing current through them. It also improves linearity, I suggest that.
20180602_165754.jpg

- - - Updated - - -

I must also explain more details I think. In my design kit, the logic transistors are 1.8V ones. Here, on the other hand, I have to pass 2.5V Vref to the resistor core. For this reason, I have to use 5V transistors (there are no 3.3V transistors in the design kit. I am using 3.3V digital signal with these 5V tolerant transistors. The downside of this 5V ones is that their Vt is large compared to 1.8V ones. The VT of the transistors I am using is around 800mV. So, I am worried that if I try to use the scheme you suggested, the switches that is going to be placed at all the R branches may fail to get that specific node pulled down or pulled up... I hope I am making sense...
 

Ok, now I see it, and actually you are right I think, sorry for misunderstanding. I didn`t build DAC with unequal branches, but it seems it is possible. It makes me suspicious that mismatch of some branches are more relevant in the final INL or DNL, but I don`t know.
It seems the point is the binary weighted numbers of switches. To reduce switch number, and area I have one recommendation. In the first branch now you are using 1 switch, then in the last branch you need 4 parallel switches. So you need 8 switches in total. But if you would use 2 series switches at the 1st branch, the total switch number would be 7. With more bits the difference is more relevant if you use series switches too and to optimize area and layout arrangement could be better maybe.
 
Hello again. It is ok, I could have explained better I suppose.

I'd like to thank you very much for the suggestion. The total switch size is now like half. (it used to have the following scheme: 1+1+2+4+8+16+32+64+128+15*256 unit cells, now 2+2+1+2+4+8+16+32+64, + 15*128 cells). Since this series switches are at the very lower branch, it is seemingly possible to do the job for pulling it to ground and passing 2.5V to the LSB without a problem.

Ok, now I see it, and actually you are right I think, sorry for misunderstanding. I didn`t build DAC with unequal branches, but it seems it is possible. It makes me suspicious that mismatch of some branches are more relevant in the final INL or DNL, but I don`t know.
It seems the point is the binary weighted numbers of switches. To reduce switch number, and area I have one recommendation. In the first branch now you are using 1 switch, then in the last branch you need 4 parallel switches. So you need 8 switches in total. But if you would use 2 series switches at the 1st branch, the total switch number would be 7. With more bits the difference is more relevant if you use series switches too and to optimize area and layout arrangement could be better maybe.
 

You are welcome, and I think you have already known if you connect 4 switches in series at the 1st branch, your area can be 4 times smaller than it was originally.
Keep cautious with linearity, 12 bit is very high!
Your LSB is like 600uV, so noise performance of your ladder and buffer have to be good, you buffer needs extreme low offset and high gain on the full output range.
Good luck!
 

Hi. Yes I know. I will also try that but 4 back to back switch may fail to bring it down properly given the voltage headroom. Will check anyways.
Although it is 12 bits, I have a max INL of 2LSB spec, funny huh, but I hope it will make things much easier.

The amplifier's gain is on the good side I'd say, around 120dB.

I completely neglected noise considerations :( The unit resistor R is around 21k. And the input resistance is between 3R and 4R I think depending on the input code with this topology. Looking from the outside, neglecting the segmented part, I think we see R regardless of the code. Can you say anything about the noise for the resistive part with these information?

I do not have any experience with noise simulation to be honest. Any help on that is greatly appreciated. I am using cadence by the way.

You are welcome, and I think you have already known if you connect 4 switches in series at the 1st branch, your area can be 4 times smaller than it was originally.
Keep cautious with linearity, 12 bit is very high!
Your LSB is like 600uV, so noise performance of your ladder and buffer have to be good, you buffer needs extreme low offset and high gain on the full output range.
Good luck!
 

The output noise matters of the R2R I think, so you should calculate with 1R.
With hand calculations you can calculate only noise power density, and you can calculate from it average power and RMS voltage. I don't know how much is your bandwidth (hold it low if you can) and the RMS value should be: Vrms=sqrt(4*k*T*B*R). But your buffer can add more noise, especially if it is low power circuit.
I suppose you can find good guides on the web to perform noise simulations, come back with specific questions if you have some.
I suggest at least run a transient analysis with added transient noise. There is a tick to enable it in the tran analysis window. Just be sure your devices generate noise (usually they have a noise flag at the properties).
What can be also important is the supply noise rejection, but with AC analysis it is easy to perform.
 

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