+ Post New Thread
Results 1 to 9 of 9
  1. #1
    Junior Member level 1
    Points: 764, Level: 6

    Join Date
    Oct 2014
    Posts
    15
    Helped
    0 / 0
    Points
    764
    Level
    6

    Why the Poly gate layer is longer than Select layer in PCell?

    I'm creating some Standard Cells: NOT, NAND, NOR... with fix parametters. For size optimization, I plan to recreate the NMOS and PMOS cell as design rule from PDK.

    I have noticed that the Poly gate layer is longer than Select layer in default PCell. In my customization, the height of Poly gate is shorter than default.

    I did check the DRC, LVS, ERC. Everything is OK. But I still do not know why the default has longer. Could anyone please explain it? Thank you very much.

    •   AltAdvertisment

        
       

  2. #2
    Advanced Member level 5
    Points: 36,547, Level: 46

    Join Date
    Mar 2008
    Location
    USA
    Posts
    5,882
    Helped
    1704 / 1704
    Points
    36,547
    Level
    46

    Re: Why the Poly gate layer is longer than Select layer in PCell?

    The active gate region (which may be the "Select" layer)
    is the intersection of poly and active. Poly extends outward
    for the gate access stub (nobody lets you put poly contact
    over active, that I have seen).



  3. #3
    Advanced Member level 1
    Points: 4,954, Level: 16
    Achievements:
    7 years registered

    Join Date
    Feb 2008
    Posts
    473
    Helped
    156 / 156
    Points
    4,954
    Level
    16

    Re: Why the Poly gate layer is longer than Select layer in PCell?

    Gate contact over active has been used for more than a decade in CMOS image sensors (pixels), and now in newer technologies.
    Gate over field poly is not the primary reason why poly extends beyond active.


    https://electroiq.com/chipworks_real.../04/10nm-6.png

    COAG (contact over active gate) – A process feature whereby the gate contact is stacked on top
    of the transistor gate rather than at its side. Intel has implemented COAG in its 10nm process –
    an industry first – thereby improving transistor density.


    1 members found this post helpful.

    •   AltAdvertisment

        
       

  4. #4
    Junior Member level 1
    Points: 764, Level: 6

    Join Date
    Oct 2014
    Posts
    15
    Helped
    0 / 0
    Points
    764
    Level
    6

    Re: Why the Poly gate layer is longer than Select layer in PCell?

    Quote Originally Posted by dick_freebird View Post
    The active gate region (which may be the "Select" layer)
    is the intersection of poly and active. Poly extends outward
    for the gate access stub (nobody lets you put poly contact
    over active, that I have seen).
    Quote Originally Posted by timof View Post
    Gate contact over active has been used for more than a decade in CMOS image sensors (pixels), and now in newer technologies.
    Gate over field poly is not the primary reason why poly extends beyond active.


    https://electroiq.com/chipworks_real.../04/10nm-6.png

    COAG (contact over active gate) – A process feature whereby the gate contact is stacked on top
    of the transistor gate rather than at its side. Intel has implemented COAG in its 10nm process –
    an industry first – thereby improving transistor density.
    Thank you all for explaining. I understand that the gate needs to extend outward the active region as @dick_freebird said. But my question is a bit different. Sorry for confusing you.

    As image below, the left side is default PCell, the right side is my customization cell. Top is PMOS, bottom is NMOS. You can see that all layer has same size except Poly layer. I have checks simple INVERTER circuit. DRC, LVS, ERC is OK. There is no problem in verification.

    Click image for larger version. 

Name:	1.PNG 
Views:	13 
Size:	18.0 KB 
ID:	147004

    In my custom cell, the Poly Layer longer than Island layer but still shorter than Select layer.

    My question is, why the default PCell needs to extend the Poly Layer when it is no need. If the Poly Layer is shorter as my custom. The total size of whole layout will be decreased.



    •   AltAdvertisment

        
       

  5. #5
    Advanced Member level 5
    Points: 36,547, Level: 46

    Join Date
    Mar 2008
    Location
    USA
    Posts
    5,882
    Helped
    1704 / 1704
    Points
    36,547
    Level
    46

    Re: Why the Poly gate layer is longer than Select layer in PCell?

    There's always a finite "poly extension of active" rule to
    ensure that the channel and the transition to, and the
    close-in isolation sidewall have an electrode in authority
    (plus alignment, litho blowout margins) over the active
    channel region. Without it, oxide charge in overlayers may
    cause edge leakage and worse yet, inconsistently so.



  6. #6
    Full Member level 2
    Points: 1,115, Level: 7

    Join Date
    Sep 2015
    Posts
    128
    Helped
    25 / 25
    Points
    1,115
    Level
    7

    Re: Why the Poly gate layer is longer than Select layer in PCell?

    What is the purpose of the Select layer and why are you wanting to create your own transistor pcells?



  7. #7
    Junior Member level 1
    Points: 764, Level: 6

    Join Date
    Oct 2014
    Posts
    15
    Helped
    0 / 0
    Points
    764
    Level
    6

    Re: Why the Poly gate layer is longer than Select layer in PCell?

    Quote Originally Posted by dick_freebird View Post
    There's always a finite "poly extension of active" rule to
    ensure that the channel and the transition to, and the
    close-in isolation sidewall have an electrode in authority
    (plus alignment, litho blowout margins) over the active
    channel region. Without it, oxide charge in overlayers may
    cause edge leakage and worse yet, inconsistently so.
    Sorry but what is "transition to"? Do you mean the transitor oxide?
    Btw, thank you for your help...

    Quote Originally Posted by rangermad View Post
    What is the purpose of the Select layer and why are you wanting to create your own transistor pcells?
    Nselect or Pselect layer indicate where the semiconductor is implanted n-type or p-type atoms, respectively. It derived by bloating the implant layer (in this case, it is Island layer)

    Because I create the standard cell, I need to make sure the MOSFET which I am using has the smallest size. I realize that the default MOSFET does not have smallest poly gate width, so I wonder the reason behind it.



    •   AltAdvertisment

        
       

  8. #8
    Full Member level 2
    Points: 1,115, Level: 7

    Join Date
    Sep 2015
    Posts
    128
    Helped
    25 / 25
    Points
    1,115
    Level
    7

    Re: Why the Poly gate layer is longer than Select layer in PCell?

    From your picture it appears as if you are measuring from a thin/thick oxide type of layer and not the P+/N+ implant layer. The implants layers will typically completely enclose the active layer and what you are measuring to does not. Your select layer could also be some type of VT implant also.



  9. #9
    Junior Member level 1
    Points: 764, Level: 6

    Join Date
    Oct 2014
    Posts
    15
    Helped
    0 / 0
    Points
    764
    Level
    6

    Re: Why the Poly gate layer is longer than Select layer in PCell?

    Quote Originally Posted by rangermad View Post
    From your picture it appears as if you are measuring from a thin/thick oxide type of layer and not the P+/N+ implant layer. The implants layers will typically completely enclose the active layer and what you are measuring to does not. Your select layer could also be some type of VT implant also.
    I think there are some confuses here...

    - There are 3 layer in this layout: Poly layer which forms the Gate, Select and Island (or active) layer which define the Source and Drain
    - The white inside border is active layer, which will be implanted N+ or P+ type. The width of device is measured according to this layer.
    - The violet layer is Pselect layer (above is PMOS)
    - The green layer is Nselect layer (below is NMOS)
    - There is no implant layer, just implant region (in 3D silicon structure). Am I wrong?

    I did compare (measure) both Select and Island layer (which you can see in the figure). My custom and the default is the same for all parametter (length, width, space between layer, inner space, outer space...). Except the Poly layer.



--[[ ]]--