Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Force deposit through testbench

Status
Not open for further replies.

rmk423

Newbie level 4
Joined
Sep 1, 2017
Messages
7
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
52
Force in Synopsys DVE

Hi,

What is the difference between these two?

1) force a 0
2) force -deposit a 0

Please elaborate.

Thanks,
RMK
 

Re: Force in Synopsys DVE

1) force a 0
-> Keep a constant 0
2) force -deposit a 0
-> Keep a constant until a change value by itself.
 

Hi,


I tried compiling a testbench.v with the below , but ended up with syntax error,

force -deposit a = 0;


How to do this?


Thanks,
RMK
 

deposit is no known Verilog keyword. You are apparently confusing simulator command language with Verilog.

- - - Updated - - -

What do you want to achieve? An initial assignment or a assignment at a specific time?
 

Re: Force in Synopsys DVE

1) force a 0
Modelsim/simulator do file command
The equivalent in Verilog is
Code:
force a = 'b0;
assuming a is in the same scope as the force command.

2) force -deposit a 0
Simulator command with no direct equivalent statement in Verilog. Though you could potentially write code that emulates the functionality by checking for a condition that would result in releasing a force command and perform the release.
Code:
release a;   // is used to end forcing a.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top