Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] HSPICE 2013 SP2 28T Full Adder Simulation Problem

Status
Not open for further replies.
M

manili

Member level 1
Joined
Sep 15, 2014
Messages
41
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,602
Hi all,

I'm trying to simulate a 28 Transistor CMOS Full Adder using HSPICE 2013 SP2. Here is the picture of what I'm trying to implement.
This is my HSPICE code:

Code: 
CMOS Full Adder
.include		'../32nm_LP.pm'
.temp			25
.param 			tech_lngth=32n
.param			vmax=0.9
.param			wnmos=64n
.param			wpmos=160n

.SUBCKT		FA		A		B		C		COUT	SUM			VSS		VDD
MPA1		VDD		A		U1		VDD		PMOS	W=wpmos		L=tech_lngth
MPB1		VDD		B		U1		VDD		PMOS	W=wpmos		L=tech_lngth
MPA2		U1		A		U2		VDD		PMOS	W=wpmos		L=tech_lngth
MPB2		U2		B		OUT1	VDD		PMOS	W=wpmos		L=tech_lngth
MPC1		U1		C		OUT1	VDD		PMOS	W=wpmos		L=tech_lngth

MNC1		OUT1	C		D1		VSS		NMOS	W=wnmos		L=tech_lngth
MNA1		D1		A		VSS		VSS		NMOS	W=wnmos		L=tech_lngth
MNB1		D1		B		VSS		VSS		NMOS	W=wnmos		L=tech_lngth
MNA2		OUT1	A		D2		VSS		NMOS	W=wnmos		L=tech_lngth
MNB2		D2		B		VSS		VSS		NMOS	W=wnmos		L=tech_lngth

MPI1		VDD		OUT1	COUT	VDD		PMOS	W=wpmos		L=tech_lngth
MNI1		COUT	OUT1	VSS		VSS		NMOS	W=wnmos		L=tech_lngth

MPA3		VDD		A		U3		VDD		PMOS	W=wpmos		L=tech_lngth
MPB3		VDD		B		U3		VDD		PMOS	W=wpmos		L=tech_lngth
MPC3		VDD		C		U3		VDD		PMOS	W=wpmos		L=tech_lngth
MPA4		U3		A		U4		VDD		PMOS	W=wpmos		L=tech_lngth
MPB4		U4		B		U5		VDD		PMOS	W=wpmos		L=tech_lngth
MPC4		U5		C		OUT2	VDD		PMOS	W=wpmos		L=tech_lngth

MNA3		D3		A		VSS		VSS		NMOS	W=wnmos		L=tech_lngth
MNB3		D3		B		VSS		VSS		NMOS	W=wnmos		L=tech_lngth
MNC3		D3		C		VSS		VSS		NMOS	W=wnmos		L=tech_lngth
MNA4		OUT2	A		D4		VDD		NMOS	W=wnmos		L=tech_lngth
MNB4		D4		B		D5		VDD		NMOS	W=wnmos		L=tech_lngth
MNC4		D5		C		VSS		VDD		NMOS	W=wnmos		L=tech_lngth

MPI2		U3		OUT1	OUT2	VDD		PMOS	W=wpmos		L=tech_lngth
MNI2		OUT2	OUT1	D3		VSS		NMOS	W=wnmos		L=tech_lngth

MPI3		VDD		OUT2	SUM		VDD		PMOS	W=wpmos		L=tech_lngth
MNI3		SUM		OUT2	VSS		VSS		NMOS	W=wnmos		L=tech_lngth

.ENDS		FA

X1			A		B		C		COUT1	SUM1	G_VSS		G_VDD		FA
X2			A		SUM1	COUT1	COUT2	SUM2	G_VSS		G_VDD		FA

vSupply		G_VDD	0		vmax
vGround		G_VSS	0		0
vA			A		G_VSS	0		PULSE	0		vmax		0.5N 		0.01N 		0.01N		10N			20N
vB			B		G_VSS	0		PULSE	0		vmax		0.5N 		0.01N 		0.01N		20N			40N
vC			C		G_VSS	0		PULSE	0		vmax		0.5N 		0.01N	 	0.01N		40N			80N

.TRAN		1P		80.5N
.END

After simulation, I try to show the result using CScope software. Everything works fine except result of the SUM when A = B = C = 1.
I'll add a pic of simulation in the attachments.

Any ideas?
 

Attachments

  • HSPICE_FA_Sim.png
    HSPICE_FA_Sim.png
    41.7 KB · Views: 250

A schematic diagram is easier to analyze than the netlist.
Don't you have this?
 

@andre_teprom,
Thanks a lot for the reply. Unfortunately I'm implementing the circuit fully in HSPICE (for learning purposes).
I don't know if there is a tool to convert HSPICE to schematic or vice versa?
 

We usually implement a circuit in a top-down approach, and so I suppose you have at least one readable scribble in the paper of that you have implemented above, preferably assigning the nodes of the netlist..
 

I added the schematic in the attachment.
Thanks.
 

Attachments

  • 28T FA.gif
    28T FA.gif
    70.3 KB · Views: 299

Copy and paste error?
Code: 
MNB4	D4	B	D5	[COLOR="#FF0000"]VDD[/COLOR]	NMOS	W=wnmos	L=tech_lngth
MNC4	D5	C	VSS	[COLOR="#FF0000"]VDD[/COLOR]	NMOS	W=wnmos	L=tech_lngth
 
  • Like
Reactions: manili

    M

    manili

    Points: 2
    Helpful Answer Positive Rating
That was awesome!!! You just solved my problem. Thanks a lot :))
Do you have any ideas why I'm getting negative output (about micro volts) sometimes? Is it OK?
 

Maybe gate crosstalk, or transient solution inaccuracy. Surely not a problem.
 
  • Like
Reactions: manili

    M

    manili

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top