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how to poll a status bit in verilog

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gary36

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Hi I am a newbie and trying to develop SPI interface to ADC. It is required to poll the end of conversion bit before reading the results. Any example code in verilog to do this. The code must wait till EOC arrives.
 

Hi,

a lot to guess.
* external ADC, connected as SPI slave?
* What ADC?
* you need to program an FPGA in Verilog as SPI master?
* EOC signal ????

*****
You talk about "code " and "poll". Both let´s me assume you think as if it is software, but you need to design hardware.
Verilog is a hardware description language.

Imagine:
SPI is just a shift register controlled by a counter.
Now the counter is disabled as long as the conversion is in progress.
--> The EOC signal just has to be fed to the ENA signal of the counter.

For sure it depends on how your SPI is implemented, the required timings, what data/signals needs to be sent to the ADC, how the incoming data are processed... and so on.

In short: we need more details.

Klaus
 

Hi KlausST

My problem is modified. Let me state the requirement. My FPGA operates on 10 MHz. I am receiving SPI CLK and Serial Data from another device. SPI CLK frequency is 100KHz.
The requirement is to sample the data at the rising edge of SPI CLK and store it in register (in FPGA). Since there are two clocks, how to design a synchronous circuit?
 

You have a 100:1 ratio between the clocks, just sample the SPI signals using the 10 MHz clock and use a 2 flip-flop synchronizer on all the SPI signals. There are quite a few examples of SPI code like that if you google for it.
 

Hi,

sadly I´m even more confused.
Before it was about to detect EOC.. now it seems to be something totally different.

Please try to draw a draft to explain what you want to do and what information you need. Please focus on one probelm only.

Klaus
 

Hi Klauss

Sorry for the confusion. Originally I was to implement logic as provided in #1 but the problem statement changed to #3. I am not clear with ads-ee solution. I was thinking that I can use always statement to register the serial data using 100KHz clock and then use 10MHz clock to synchronize the data. Is this approach OK? I need fully synchronous design
 

Run the SPI signals through 2 Flip-flops (clocked by the 10 MHz) now the outputs from the 2nd FFs are synchronous to your system clock.

Use edge detection on the synchronized (above) SPI clock (the 100KHz clock) to determine either the rising or falling edge to determine when bits are transferred.

Pretty easy stuff, do a search for Verilog/VHDL SPI code, I'm sure you'll find something.
 

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