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  1. #1
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    Pb with VNC2 and SPI interface

    Hi,

    i am working on a little project based on a PIC18F4550 and a VNC2 chip, both connected via the SPI interface (in VNC1 compatible mode). I began this project with 2 evaluation boards, one for each chip (the V2EVAL board for the VNC2 chip).

    As all worked fine, i decided to go to the next stage by creating a PCB prototype. After soldering all components, i tested the board and faced a problem: that didn't work.

    With a debugger, i found that data coming from the VNC2 chip were wrong: they were shifted one bit to the left, losing the seventh bit. Sending data to the VNC2 worked, but not receiving data. I firstly thought about a wrong PCB design and passed much time in this way, but i discovered a strange thing with my scope.

    Look at the picture below (signal names are relative to VNC2 chip): It show a read cycle by the PIC. The data sent to the PIC is 0x88 and this is incredible. Instead of beginning to transfer data at the fourth rising edge clock cycle, VNC2 chip begins at the third, ignoring the addr bit ! This doesn't work as expected: according to the datasheet, a read transfer begin with a start bit, a direction bit and an addr bit after what VNC2 transfer the seventh bit of the data, followed by the sixth bit and so... In the point of view of the PIC, writing data works, but not reading.

    Now, if i remove the clock cycle relative to the addr bit for a read transfer (not the write transfer), it works fine as expected by my design.

    So, without this little modification, it works with the evaluation boards like the datasheet explains; And with this modification, it works with my PCB prototype but not as explain by the datasheet. Same chips, but different behavior. Really ? Not, because there is a little difference: the V2EVAL board has a VNC2 Rev B chip, and my prototype has a VNC2 REV C chip.

    Is it possible that the Revision C has a bug that revision B doesn't have (According to FTDI, the only difference is an improvement against ESD protection) ? Or is there really a bug i my PCB prototype design ?

    Can someone confirms this bug ?

    Thanks,

    willy.

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  2. #2
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    Re: Pb with VNC2 and SPI interface

    What you describe (all the talk about read transfers, start bit, direction bit, 'addr' bit etc.) sounds more like I2C than SPI. Are you sure that you have programmed the correct protocol?
    Also the clock bit is totally rubbish and nothing like I have had generated with either a PIC or the VNC2. For a start there are more than 8 clock pulses while the CS is high (typically the CS line is active low) and of varying sizes. Then they are not of regular duty cycle (normally they are 50% duty cycle).
    I don't know what you mean by removing the clock cycle relative to the 'addr' bit. Are you bit-banging the SPI exchange rather than using the VNC2 hardware?
    Susan



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  3. #3
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    Re: Pb with VNC2 and SPI interface

    Hi,

    I use the VNC1L SPI legacy interface which is a FTDI protocol. As the SPI module of the PIC doesn't handle this protocole, i bit-bang its SPI interface. The PIC is the master, the VNC2 the slave. The PIC generates CS, CLOCK and SDI (MOSI).
    The clock signal is generated when a transfert is required. I don't think it is important to have a 50% duty cycle. Even with a 50 % duty cycle, it does the same.

    I just read the datasheet (supply below) again and i don't understand: look at the page 48, figure 6.14. This is what i have with my the scope, so no problem at all it works as expected. But now, i don't undertsand:

    The VNC2 begin to transfert data during the 3 bit command phase. But how can it begin to transfer data at the same rising edge of the clock it is supposed to acquired the addr bit, because this bit determine the data to transfer ?


    Thanks,

    Willy.



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    Re: Pb with VNC2 and SPI interface

    Hi,

    I use the VNC1L SPI legacy interface which is a FTDI protocol.
    You are corrct, this is not a standard 8 bit oriented SPI protocol.
    May I ask why you use especially this "non standard SPI protocol"? Why donīt you use the standard full duplex SPI protocol?

    Klaus
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  5. #5
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    Re: Pb with VNC2 and SPI interface

    Hi,

    I use this protocol because i began this project with a VNC1 chip, then upgraded to VNC2 to change some things in the V2DAP firmware. As this part of the software is working fine, i didn't change it.

    By removing one cycle, SPI transferts work fine now, but i just want to understand why, because according to what i have read in the datasheet, it shouldn't.

    Thanks,

    Willy.



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  6. #6
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    Re: Pb with VNC2 and SPI interface

    If it is working now then that is good. I certainly agree that you may be better off by switching to the standard (i.e. VNC2) SPI protocol.
    I can certainly understand why you want to know what is going wrong though.
    The data sheet you provide clearly shows the data being sampled on the rising clock edge and the falling edge begin used to trigger any internal changes.
    Given the shape of the clock pulses, this may be causing some issues within the VNC2 firmware and I would suggest that you try to generate a clock signal that has more of a 50% duty cycle.
    Also, is the timing of the SS line correct. Your image a few posts back shows 16 clock pulses, 2 before the SS line goes high, 11 while it is high and 3 after it goes low again.
    Finally it is hard to tell from your image exactly what command you are trying to give the VNC2. The 'Start' bit has to be high and it looks like to have the R/W bit high (read from the slave) but I can't tell what the 'Addr' bit should be as the rising edge of the clock seems to coincide with the falling edge of the 'DI' trace.
    Susan



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