Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Divison by 2 syntesizable RTL coding

Status
Not open for further replies.
S

sky_above

Member level 2
Joined
May 14, 2018
Messages
43
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
375
Will the following rtl do the divison by 2 of the input after synthesis ?


Code: 
module div_2(in0,out0)
input in0;
output out0;
assign out0=in0>>1;
endmodule
 

Will the following be a correct code then for division by 2 of the input?

Code: 
module div_2(in0,out0);
parameter k=6;
input [k-1:0] in0;
output [k-1:0] out0;
assign out0=in0>>1;
endmodule
 

sky_above said:
Will the following be a correct code then for division by 2 of the input?
Click to expand...

This type of question can be answered by yourself, you have already got the recomendation of a website where you can test your code online yourself, once you have given the enigmatic pretext that "it is not possible" to use any free FPGA vendor's tools.

This thread will closed due to your insistence on asking others to do something that would be expected of someone working/learning this subject, to do by himself.

You will also be formally notified to stop this practice, and be aware that after some amount of infractions there is the risk of the system banning you automatically, irrespective of anyone will.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top