sky_above
Member level 2
Realization of D flip flop by basic gates from library while synthesizing
With a rtl of a D-Flipflop how can the synthesis tool be instructed so that the synthesis tool while synthesizing that rtl does not pick up the D-Flipflop library cell directly but realizes the D-Flipflop by collection of basic NAND, NOR , INVERTER gates from the library?
With a rtl of a D-Flipflop how can the synthesis tool be instructed so that the synthesis tool while synthesizing that rtl does not pick up the D-Flipflop library cell directly but realizes the D-Flipflop by collection of basic NAND, NOR , INVERTER gates from the library?