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sky_above

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Realization of D flip flop by basic gates from library while synthesizing

With a rtl of a D-Flipflop how can the synthesis tool be instructed so that the synthesis tool while synthesizing that rtl does not pick up the D-Flipflop library cell directly but realizes the D-Flipflop by collection of basic NAND, NOR , INVERTER gates from the library?
 

Re: Realization of D flip flop by basic gates from library while synthesizing

You just have to define your ff the way you want. There us absolutely no reason the synthesis tool would pick the slower, less efficient way of doing it.
 

Re: Realization of D flip flop by basic gates from library while synthesizing

sky_above said:
With a rtl of a D-Flipflop how can the synthesis tool be instructed so that the synthesis tool while synthesizing that rtl does not pick up the D-Flipflop library cell directly but realizes the D-Flipflop by collection of basic NAND, NOR , INVERTER gates from the library?
Click to expand...

synthesis tool will never build a flip-flop out of basic gates. it will pick the dff from the library.
 

Re: Realization of D flip flop by basic gates from library while synthesizing

You could make your own block-level FF-as-gates design
and then refer to this explicitly in higher level blocks' code,
perhaps?
 

Re: Realization of D flip flop by basic gates from library while synthesizing

You could 'fool' the tool, but whatever flip-flop you get out of it will be so poorly designed. Not to mention the STA analysis is gone, it simply wouldn't work because it would see combinational loops.
 

Re: Realization of D flip flop by basic gates from library while synthesizing

It is simply that you can not do with a synthesis Tool.

A group of people will take care a NAND level of standard cell which can circuit design, or libabry design team.
The others ( like you ) will use their output ( as called libraries ) to do synthesis.
That flow makes things be easier.

I am not sure but maybe you can see the NAND level in case you use some Spice ( Hspice, Pspice ... ) simulation tool.
 

Re: Realization of D flip flop by basic gates from library while synthesizing

ThisIsNotSam said:
You could 'fool' the tool, but whatever flip-flop you get out of it will be so poorly designed. Not to mention the STA analysis is gone, it simply wouldn't work because it would see combinational loops.
Click to expand...

Suppose you are synthesizing a big design where there are many D-Flipflops along with some combinational logics. Suppose we synthesize that big design such that all D-Flipflops are realized by basic NAND, NOR, INVERTER and not by library D-Flipflop cell.
How will you get combinational loops? Because a flipflop have a combinational loop inside it by its design. Will not the tools like the STA tool understand that these are all flip-flops when it analyzes the whole design?
 

Re: Realization of D flip flop by basic gates from library while synthesizing

Are you actually asking about ASIC design? In this case, flip flops from the library are already representing the minimal gate level implementation and there's absolutely no use of defining it differently. If the question is however about FPGA, don't expect useful behaviour of your homemade FFs.
 

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