Output combinational output and valid sequential

Can the output from a digital system be such that the output is from the output of a combinational logic inside the design and the valid for the output be sequential as the valid is generated from a sequential logic which is inside the design?

I suppose you could do this, but why? The sequential circuit would have to be aware of the propagation delays of the combinational logic and generate its output accordingly.

barry said:

I suppose you could do this, but why? The sequential circuit would have to be aware of the propagation delays of the combinational logic and generate its output accordingly.

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This is because the date is coming from the FSM combinational block and the valid is coming from the output of the fsm. If The data need to be in the same clock cycle as per with the valid then we waste a register by registering the output data with that register. Here valid output data comes before the Valid signal for the data. The fsm is a Mealy fsm.

The post #1 has a typo which is corrected below:
Can the output from a digital system be such that the output is from the output of a combinational logic inside the design and the valid for the output is sequential as the valid is generated from a sequential logic which is inside the design?

Yes this is possible, however, if there are glitches in combinational output, those glitches will be propagated to downstream logic when valid signal is asserted. If downstream logic can tolerate glitches, sure you can do this.

What happens downstream? If you are using the valid signal to synchronously latch the combinational signal the tool should take care of synchronizing everything.

swabhi812 said:

Yes this is possible, however, if there are glitches in combinational output, those glitches will be propagated to downstream logic when valid signal is asserted. If downstream logic can tolerate glitches, sure you can do this.

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The downstream logic only should accept the combinational output when the Valid is high. So only when the valid is high the downstream logic should accept the combinational output data. So downstream logic is only getting data without glitch.

What are you trying to say? You said the same thing two different ways. Re-read post #5.

barry said:

What are you trying to say? You said the same thing two different ways. Re-read post #5.

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sounds like an academic exercise with no real purpose

barry said:

What happens downstream? If you are using the valid signal to synchronously latch the combinational signal the tool should take care of synchronizing everything.

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The downstream logic will also run with the same clock with the driving logic. So it is all synchronous here. Please write back for if not clear.
The valid signal is used to synchronously latch the combinational signal. Which tool are you talking here?

sky_above said:

The downstream logic will also run with the same clock with the driving logic.

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You're extremely unclear. You said you've got combinational logic- that doesn't use "the same clock", it doesn't use ANY clock. But the fact that your combinational signal is synchronously latched makes everything ok. There is nothing unusual here.