IC design and MOSIS C5 technology for newbie

Hello
I am passionate about electronics and for a hobby project I would like to design (and then realize) an IC.

I have no background in the implementation of IC and VLSI design, just some knowledge, but no real project.

So excuse me if I write some nonsense.

If I understood correctly, I could make my IC with a technology called C5 provided by MOSIS.

These are my questions:


1) Is there a way to create a transistor (PMOS or NMOS) with finely tuned Vth voltage, using MOSIS technology?


2) On which parameters do I have to act in order to realize a MOSFET with a desired Vth voltage?


3) Do free programs allow you to act on these parameters? Or are they forced to use the default dimensions for the reference technology?


4) Which program do you recommend? I'm looking for Electric, Magic VLSI and LASI. Which according to you allows you to work better?

5) I have seen that these programs allow to manage a supply voltage (usually + 5V). But is this a characteristic of the reference program or technology (C5)? If I wanted to implement devices capable of operating with dual voltage (eg + 5V, -5V) or with lower voltages (3.3V), could I do it?

You do not get to set the Vth, only pick from a limited
"palette" and if I recall in ON C5 there are only "regular"
devices.

Lower single voltage is OK. +/-5V will violate well breakdown
and BVox.

Expect $20K or so, for a multiproject access and a handful
of dice if you go to ON directly; no idea what MOSIS fees
may be, in addition or instead.

ON has decent PDKs for Cadence and Silvaco, I'd bet
Tanner does, but even the latter two are $20K a seat-year
or so. LASI I believe has a kit and is good-to-go with a
decent WinSPICE connection (LASI free, WinSPICE free-ish
although the guy would like you to license (cheap enough).
Be aware that LASI lacks any LVS and all you can do is
either verify by SPICE (functionality) or find a third party
SPICE-vs-SPICE equivalence checker (LVS using the SPICE
extract).

dick_freebird said:

You do not get to set the Vth, only pick from a limited
"palette" and if I recall in ON C5 there are only "regular"
devices.

Lower single voltage is OK. +/-5V will violate well breakdown
and BVox.

Click to expand...

Ok, at this point I have another question:
Is it possible, however, to create some MOSFETs with the simulation programs that have the desired characteristics (Vth) and simulate the functioning (even of entire circuits made with these devices)?

In this case, thinking of an industrial realization (not hobbyist), these simulated devices, will then be feasible?

Sure, you can alter the VT and other channel attributes
as you like, in simulation. Multiple VTs in a single flow is
feasible. I've worked in a technology that had 4 VTs per
species (Regular, Low, Intrinsic, Depletion for both N and
P). Some were not real great as far as process control
or short channel behaviors but they existed.

The trick is getting the fab to want to turn the knobs
initially, and getting the fab to qualify the new flow for
production.

Ok, Thanks. I return now on same question.

I now use Magic and I realized simple mosfet layout.
For change the Vth, can I do it directly from Magic?

Or do I have to export the layout and set the VTh from the spice model?

You cannot change the -real- manufactured device VT.

You can do whatever you like to the SPICE model but
then you will be simulating a fiction that can only be
realized by time, cash and a whole lot of bickering.

MAGIC is nothing but layout and verification, it has no
relation to SPICE other than through the extracted
connectivity. Don't try to pound screws, know your
tool.

My problem is to create a layout (MOSFET / CMOS) that contains all the parameters to be implemented on silicon.
One of these parameters is definitely the threshold voltage.

I do not know how to proceed, I have no experience and I do not know what is the way to do it.
I thought it was enough to draw the layout and also specify the parameters to change (for the VT also the thickness of oxide).

But how do you proceed?

clros said:

I thought it was enough to draw the layout and also specify the parameters to change (for the VT also the thickness of oxide).

Click to expand...

Foundries don't change their technology for you. You need to find a technology that meets your requirement.

Ok, but is there a way to make layouts that are technology independent?

clros said:

Ok, but is there a way to make layouts that are technology independent?

Click to expand...

No. Layers and layout rules are specific to one technology. IC design is really different from the degrees of freedom that you have in PCB circuit design.

The only "technology independent" designs I know of
(and don't know much) are the SCMOS "lambda rules"
scalable CMOS libraries. Maybe NCSU is the hub for that,
do not recall.

But this is more an aspiration than a fact, and less of
a fact the lower in gate length you go - process features
roll in and proliferate as you get shorter and shorter,
which was not really the case above 0.5u or so.

A question is, if you can barely afford one multiproject
run, what will you ever do with the "scalable" design
in the future? Neat ideas are one thing, spending a
lot of effort on a given one is another thing entirely.
Be sure you are working to a plan, not to a notion.