sky_above
Member level 2
For a D Flipflop with Enable how the else part can be coded? Generally the rtl of a D-Flipflop with enable are as below and it does not show an else part. How to take care then to avoid latch generation ?
Code Verilog - [expand] 1 2 3 4 5 always @(posedge clk or negedge reset ) if (~reset) Q<=1'b0; else if (Enable) Q<=d;