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D Flipflop with enable does not have the else part in RTL in the if-else statement

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sky_above

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For a D Flipflop with Enable how the else part can be coded? Generally the rtl of a D-Flipflop with enable are as below and it does not show an else part. How to take care then to avoid latch generation ?
Code Verilog - [expand]
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5

always @(posedge clk or negedge reset )
  if (~reset)
    Q<=1'b0;
  else if (Enable)
    Q<=d;
 

edge triggered always blocks do not create latches.

If there is no else clause the Q value does not change (i.e. it holds the last value that was assigned)

The equivalent (and more verbose) version of the code you posted is:
Code Verilog - [expand]
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always @(posedge clk or negedge reset )
  if (~reset)    Q<=1'b0;
  else if (Enable)    Q<=d; 
  else  Q <= Q;
 

Latches are generated in combinational (level sensitive event triggered) always block. It's just fine this way.
 

FvM said:
Latches are generated in combinational (level sensitive event triggered) always block. It's just fine this way.
Click to expand...
According to Verilog LRM for the procedural assignment Q<= d here, the Q will have to hold the earlier value when Enable=0. So in this case the synthesis tool will try to generate a flipflop as the flipflop will hold the previous value when Enable =0 and also the synthesis tool will not synthesize latch as the always block is edge sensitive and not level sensitive Is this that is the reason for latch not being generated out of this code?

Will there be edge sensitive enable flipflops in library to realize the following edge sensitive RTL for D Flipflop ?
Code: 
always @ (posedge clk or negedge rest or posedge enable)
if (~reset)
Q<= 1'b0;
else if (enable)
Q<= d;
 

Your first question has already been answered in both replies.

sky_above said:
Will there be edge sensitive enable flipflops in library to realize the following edge sensitive RTL for D Flipflop ?
Code: 
always @ (posedge clk or negedge rest or posedge enable)
if (~reset)
Q<= 1'b0;
else if (enable)
Q<= d;
Click to expand...

If intended as DFF description, it's erroneous. According to Verilog rules, enable will be implemented as second asynchronous signal. Because the design is missing code to be executed on the clk edge, no DFF will be implemented, only a latch. To generate a DFF with enable input, "posedge enable" must not appear in the event list, the correct code is in post #1 and #2.

Please review the DFF template description in this previous post https://www.edaboard.com/showthread.php?377340-Unknown-Clock-Signal&p=1616541&viewfull=1#post1616541

- - - Updated - - -

Superficially the result seems to contradict the previous statement
edge triggered always blocks do not create latches
Click to expand...
But the code has no valid edge triggered event specification.
 

FvM said:
Your first question has already been answered in both replies.
Click to expand...

Is my following reasoning correct to correctly and completely answer my first question in post #1?

According to Verilog LRM for the procedural assignment Q<= d here, the Q will have to hold the earlier value when Enable=0. So in this case the synthesis tool will try to generate a flipflop as the flipflop will hold the previous value when Enable =0 and also the synthesis tool will not synthesize latch as the always block is edge sensitive and not level sensitive Is this that is the reason for latch not being generated out of this code?
 

It's more simple. The below code already implements a DFF 
Code Verilog - [expand]
1
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always @(posedge clk )
  Q<=d;
 

FvM said:
It's more simple. The below code already implements a DFF 
Code Verilog - [expand]
1
2

always @(posedge clk )
  Q<=d;
Click to expand...

But it will be a flipflop without a reset.

I am getting puzzled. So can you please answer the below question which was asked in post # 6?

Is my following reasoning correct to correctly and completely answer my first question in post #1?

According to Verilog LRM for the procedural assignment Q<= d here, the Q will have to hold the earlier value when Enable=0. So in this case the synthesis tool will try to generate a flipflop as the flipflop will hold the previous value when Enable =0 and also the synthesis tool will not synthesize latch as the always block is edge sensitive and not level sensitive Is this that is the reason for latch not being generated out of this code?
 

So in this case the synthesis tool will try to generate a flipflop as the flipflop will hold the previous value when Enable =0
Click to expand...
I think, the conclusion is incorrect or at least misleading in so far that a flipflop won't be generated only in this case, but in any case with or without enable, with or without reset. But also in this case.

The other part has been answered before in post #2 and #3: An edge sensitive always block always generates a flipflop and never a latch.
 

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