What kind of transistor is best optimized for short term power dissipation?

Hi - I'm interested in making a active clamping circuit to reduce spikes seen by sensitive electronics on a noisy supply line. Essentially think TVS/zener but with better tempco, steeper IV curve, etc. Just like a TI flat clamp, but higher power capabilities.

One thing that I was not sure about is which sort of transistor would be best. My first thought was an SOA optimized N-FET like some of the nice Nexperia parts. But are there other transistor types I should be considering? I had trouble finding SOA curves for BJTs. Is it possible they would work better for this? Or something else?

Thank you!

Hi,

I had trouble finding SOA curves for BJTs.

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Usually this should be included in the datasheet.

Which device (datasheet) particularly are you looking at?

Klaus

KlausST said:

Hi,


Usually this should be included in the datasheet.

Which device (datasheet) particularly are you looking at?

Klaus

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Hi Klaus - I looked at a few BJT datasheets and they simply didn't have an SOA curve.

After seeing your message - I did some more looking and it seems like some newer parts do include SOA curves.

So far I'm seeing drastically higher SOAs for FETs than BJTs. The shorter pulses (1ms and less) seem to all have very low limits - I believe those are bond wire limitations typically - so maybe BJTs are not as easy to optimize for that or something?

The 40V FET I'm looking at can handle 600A for short durations (dependent on Vds, of course). All the BJTs I've seen have been more like 50A.

The 40V FET I'm looking at can handle 600A for short durations (dependent on Vds, of course)

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I doubt that. Can you tell me the part number ?

To dampen a power peak on the transistor itself, I would look for some that had a metal body as thick and wide as possible, as this would be the first thermal barrier to be traversed by the heat emanating from the p-n junction toward dissipator. In any case, by the extreme requirements presented above, it would be more plausible to consider an intermediary device to dissipate some of that energy.

CataM said:

I doubt that. Can you tell me the part number ?

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Take a look at figure 11 on the NVMFS5C410N datasheet. 900A.

The part I'm looking at is not released so I cannot post datasheet - but 600A is not unreasonable.

- - - Updated - - -

To dampen a power peak on the transistor itself, I would look for some that had a metal body as thick and wide as possible, as this would be the first thermal barrier to be traversed by the heat emanating from the p-n junction toward dissipator. In any case, by the extreme requirements presented above, it would be more plausible to consider an intermediary device to dissipate some of that energy.

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With fast transients (<1ms) I think the size of the silicon is more important than the size of the body, no? That had always been my impression. Agreed that heavy metal bodies will be helpful for slower transients (100ms+). Not sure where the dividing line there is.

O.K. I saw afterwards that the MOSFET is a low voltage one.

Anyway, you can see that the graph is for Tc=25ºC. So you need to derate your peak current.

CataM said:

O.K. I saw afterwards that the MOSFET is a low voltage one.

Anyway, you can see that the graph is for Tc=25ºC. So you need to derate your peak current.

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Sure, I agree. But the point of this thread is that I'm wondering if I'm only going to find nice SOA curves like that on FETs, or if any other transistor types have similarly high SOAs.

So you want SOA in BJTs ? See e.g. this one. You can find many more using the manufacturer's selection guide/web selection tools.
https://www.onsemi.com/pub/Collateral/2N6338-D.PDF

CataM said:

So you want SOA in BJTs ? See e.g. this one. You can find many more using the manufacturer's selection guide/web selection tools.
https://www.onsemi.com/pub/Collateral/2N6338-D.PDF

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Hi - I want to know what type of transistor can be most optimized for SOA. So far it seems like FETs can be way, way better for SOA. But nobody has confirmed this. For example, for short pulses (what I'm most concerned about) - that BJT can do 50A. The FET I linked to earlier can do 900A... (and is a much smaller device)

I have not found a BJT that has an impressive SOA yet.

uoficowboy said:

I think the size of the silicon is more important than the size of the body, no? That had always been my impression

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If the die size were often available on datasheets this would be a feature easiest to be assessed, although heating effectively happens most at the p-n junction; at least the metal case is something we can see; Anyway, if I'm not wrong, silicon is not so good thermal conductor as the metal of its package.

In answer to the original Qu: the largest one that will fit.

One question is, what is the "accessible volume" for
the thermal pulse. There are thermal time constants
that vary with distance (or vice versa, remote heat
sink contributes nothing during a short pulse). How
sparse or frequent the spikes / high level noise is a
key question, along with the pulse width & height.

Another device-design question, given this, is how
uniform the close-in heat accrual is. This also goes to
to the device operating point. For example a MOSFET
in linear operation ("on", full Vgs) dissipates most of
the power in the drift region, which is uninteresting
bulk silicon (hard to hurt), full die area and closer to
the package heat mass with its nice low thermal
impedance and thermal time constant. In saturation,
much dissipation is up in the frontside "neck" and
this feature occupies only a modest fraction of the
chip area (so more concentrated / nonuniform) and
close to critucal fragile features. As you would be
commutating the clamp device after the fact, the
device will pass through a region where the power
is dissipated in the neck regions on its way to the
fully-on case (if indeed it ever gets there - power
MOSFETs aren't exactly sporty with all that Cgd,
which drags out switching risetimes).

Might consider eGaN FETs if you want fast acting.

Bipolars have one nice attribute, which is the very
small voltage swing at the base between "off" and
"on". For equal (Cds+Cdg) and (Cje+Cjc) the drive
problem will be easier for a 0.7V BJT base swing
than a 5-10V MOSFET gate swing, at least in terms
of getting a risetime on the clamp that's fast enough
to do any useful shunting.

Another consideration that relates to clamp sizing,
is what limits the current. Putting a hard clamp up
against a stiff source means something stanky in
short order. What about a right-sized line choke,
if the noise is incoming rather thanself-generated?
Maybe knock a trailing zero off that current rating?

What topology for the circuit. I picture a zener between the gate and drain? I've made an SCR crowbar with that basic topology and it was quite effective at clamping large inductive loads. C helped limit dV/dT in that case.

If GAN is used turning on the gate quickly while also protecting it would be tricky.

Might Rdson be a clue about the die size (even though its basically irrelevant in this application)?

@ asdf44, power dissipation is the clue to die size on any data sheet... look at modern GaN fets - no power dissipation to speak of, look at an old Si mosfet, 1200V 20A, > 600W dissipation ...

larger die allows larger area to contact eventual heatsink, lower thermal resistance, higher pulse absorption, etc, ... smaller die - all the reverse ...