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D flip flop RTL without Qbar

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sky_above

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When a Dflipflop RTL is written we never assign the Qbar ouput of the flipflop. How does the synthesis tool then choose a Dflipflop cell which has a Qbar output also from the library?
 

The logic after the flop may required the inverted value, and so the Qbar is used instead to reduce the logic count.
 

rca said:
The logic after the flop may required the inverted value, and so the Qbar is used instead to reduce the logic count.
Click to expand...

How does it answer the question in post #1?
 

do you already translate your RTL code in logic gate?
do you see some optimization by removing two consecutives inverter?
 

rca said:
do you already translate your RTL code in logic gate?
do you see some optimization by removing two consecutives inverter?
Click to expand...

There is no Qbar in the RTL. Why then the rtl synthesizes to a D flipflop with a two outputs names q and qbar from the library?
 

Not gate push back during synthesis will move any inversions through logic to be generated somewhere else.

e.g. the simple divide by two circuit.
Code: 
always @(posedge clk)
  q <= ~q;

could be synthesized to..
Code: 
dff ff1 (.q(q), .d(d), .c(clk));
inv inv1 (.o(d), .i(q));
but with a q_bar available and not gate push back..
Code: 
dff ff1 (.q(), .q_bar(q_bar) .d(q_bar), .c(clk));
inverter is no longer required by using the inverted q output.
 

If some logic need the inverted or not of the value. For sure the cell designer are not stupid and the logic synthesizer uses than kind of flops.

I guess in your RTL code you do not code the carry bit of each intermediate addition bit, but the ADDER cell has only a carry and sum output.
 

At the gate level, a DFF is made of cascaded inverting gates and transfer gates. So either if you expose it or not, there will be an internal qbar node.
 

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