Cell Characterization Determining Slew vs Capacitive Values for Templates

Hi

I am using Cadence Liberate for standard cell characterization (tsmc 40nm). I am not certain about the values we should put into the delay and power templates of the tcl script. I can see that they are given with respect to the slew values against finite capacitive loads of the gate. So in the first place, how do we determine the slew and load value combinations for a given cell to complete the template ?

One paper has defined that, the mean (or central index of load indices) capcitive load should be the corresponding FO4 load of the gate. So if we characterize an inverter cell, this is 4x the input capacitance of the inverter. Then the central index of slew values is essentially the slew observed for the FO4 load. The other indices are halved to the left of the mean and doubled to the right of the mean. Does this sound reasonable ?


Thanks in advance
Anuradha

ranaya said:

Hi

I am using Cadence Liberate for standard cell characterization (tsmc 40nm). I am not certain about the values we should put into the delay and power templates of the tcl script. I can see that they are given with respect to the slew values against finite capacitive loads of the gate. So in the first place, how do we determine the slew and load value combinations for a given cell to complete the template ?

One paper has defined that, the mean (or central index of load indices) capcitive load should be the corresponding FO4 load of the gate. So if we characterize an inverter cell, this is 4x the input capacitance of the inverter. Then the central index of slew values is essentially the slew observed for the FO4 load. The other indices are halved to the left of the mean and doubled to the right of the mean. Does this sound reasonable ?


Thanks in advance
Anuradha

Click to expand...

The extremes of your characterization tables are usually impossible values, way below FO1 for the low and hundreds of pFs for the high. It works because intermediate values are interpolated.

What I have seen more recently in the industry is the use of 7 values. There is no fixed relationship between them, it's not always 2x or 1/2. If you have access to a commercial std cell library for the node you are working with, I'd suggest to follow whatever structure they have used.

You have to go through some basic exercise for selecting slew and load. It has to be done per Vt type of the standard cell at each PVT condition.
a) minimum slew: Take the fastest inverter(highest Drive) loaded by the smallest drive inverter with some approx. wireload. The transition time at the input of the slow inverter is the smallest slew you need.
b) maximum slew : estimate the maximum clock frequency ( by calculating the max. operational frequency using two back to back flops running with single clock). you have to estimate 10% of clock cycle as the max. transition time. then put inbetween points using fanout 1, 2, 4, 8 etc depending on how much point you need.
c) Min load : input cap + wireload of the smallest inverter.
d) Max load : should be the as high so that it doesnt violate maximum transition time.

There are just some simple guidelines. most companies tune their methodology by generating these data from a sample of gates in the design to come up a reasonable set of loads/slew for characterization.

Hi, thanks ThisIsNotSam, artmalik for your responses.

1. So for the different process corners, we should have different model parameters extracted from the pdk spice model for devices i.e. Best, typical and worst ?
2. In the case of 1.), as well as at lower supply voltages, we need to re-evaluate the slew values for the given loads by mixed signal simulations ? am I right ?

Anuradha

ranaya said:

Hi, thanks ThisIsNotSam, artmalik for your responses.

1. So for the different process corners, we should have different model parameters extracted from the pdk spice model for devices i.e. Best, typical and worst ?
2. In the case of 1.), as well as at lower supply voltages, we need to re-evaluate the slew values for the given loads by mixed signal simulations ? am I right ?

Anuradha

Click to expand...

Yes, you need to do this exercise for all combinations of process corners, temperature, and voltage that you care about.

Hi, further extending my inquiry......
I hope, both of you can give me an insight to this.

1. It appears that Liberate also utilizes NLDMs for characterization, how accurate is NLDM for tech nodes below 65 nm ? Is it widely used in Industry ?
2. Can we consider the highest index in capacitive loads to be the maximum load a cell can drive ? Is this an indication for the cell's drive strength ?

Thanks
Anuradha

ranaya said:

Hi, further extending my inquiry......
I hope, both of you can give me an insight to this.

1. It appears that Liberate also utilizes NLDMs for characterization, how accurate is NLDM for tech nodes below 65 nm ? Is it widely used in Industry ?
2. Can we consider the highest index in capacitive loads to be the maximum load a cell can drive ? Is this an indication for the cell's drive strength ?

Thanks
Anuradha

Click to expand...

1. NLDM is still ok for most tasks. Even 16nm libraries still come with NLDM .libs. It's probably a bit pessimistic to compensate for inaccuracy.
2. The max load is typically way beyond a FO4 type of load. Do not confuse a capacitive load used for modelling with a real circuit limitation.