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Clock gating and cdc on clock_req

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stanford

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clock_request is sent asynchronously and could have glitches, as it is a big combo logic with many conditions feeding into it from different clocks.

1. How should I use this clock_request safely to ungate/gate the clock from cdc perspective?
2. What can be done to help this situation?
 

Use state-of-the-art synchronizers and sample the gate signal at the inactive clock edge.
 

FvM said:
Use state-of-the-art synchronizers and sample the gate signal at the inactive clock edge.
Click to expand...

How do you sample the gate signal synchronously? This signal is async (not flopped as there is no clk), and has multiple clk source generating this clk request.

i.e
clk_req = a // a is async signal
|| b || c; // b,c is a sync signal

how do you use clk_req in clk gate? clk_req can be glitchy and we cant just dsync it before using as enable to clk gate.
 

we cant just dsync it before using as enable to clk gate.
Click to expand...
You surely can do exactly this. If not, there's probably a lack of specification.

What is the expected behavior of the individual signals OR-ed to clk_req, what should be the resulting signal if they are changing at arbitrary times? Either the glitches have to be accepted by design, resulting e.g. in single clock cycles gated on or off. Or clk_req has to be filtered before being send to the gate circuit.
 

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