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Schematic Extraction of Standard Cells and AMS

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ranaya

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Hi All,

I am working with tsmc 40nm pdk and would like to analyze their standard cell libraries (in schematic or layout) for mixed signal simulations (AMS). However, it appears that, the distributors do not provide cadence OA libraries for std cells nor transistor level netlists. When I import the relevant .lef files, only the abstract view of the layout is visible (metal 1 layer routes). The provided verilog netlist can only import symbol views of the cells. So under the given conditions, is performing AMS on this std cells in virtuoso not possible at all (atleast the schematic extraction)?

Thanks in advance
Anuradha
 

.lef / .def are for autorouting and synthesis, you want to
find a verilog or veriloga library that corresponds to the
available symbols. If verilog, this might be a monolithic
library file I guess, rather than singlets colocated with the
symbols in their library hierarchy.

Seems to me that the synthesis library provider would
also be the one to ask for simulation views of any sort.

I have seen other stdCell libs which lack schematic
views, and consider that lame. But it's not abnormal
unfortunately.
 

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