ranaya
Advanced Member level 4
Hi All,
I am working with tsmc 40nm pdk and would like to analyze their standard cell libraries (in schematic or layout) for mixed signal simulations (AMS). However, it appears that, the distributors do not provide cadence OA libraries for std cells nor transistor level netlists. When I import the relevant .lef files, only the abstract view of the layout is visible (metal 1 layer routes). The provided verilog netlist can only import symbol views of the cells. So under the given conditions, is performing AMS on this std cells in virtuoso not possible at all (atleast the schematic extraction)?
Thanks in advance
Anuradha
I am working with tsmc 40nm pdk and would like to analyze their standard cell libraries (in schematic or layout) for mixed signal simulations (AMS). However, it appears that, the distributors do not provide cadence OA libraries for std cells nor transistor level netlists. When I import the relevant .lef files, only the abstract view of the layout is visible (metal 1 layer routes). The provided verilog netlist can only import symbol views of the cells. So under the given conditions, is performing AMS on this std cells in virtuoso not possible at all (atleast the schematic extraction)?
Thanks in advance
Anuradha