Timing through the d pin

1. Is timing through the d pin only for latches?
2. Why do such paths exist? (i.e d pin of latch -> o pin of latch -> logic -> d pin of flop)

the latch is level sensitive. so there is an arc from d to q in latch when en =1. the flop is edge sensitive so there is nothing like d-to-q. it is depended on the clock. So you have clock to q.

there will be an arc for every input to output such the input transition causes an output transition depending on the states of other pins.

artmalik said:

the latch is level sensitive. so there is an arc from d to q in latch when en =1. the flop is edge sensitive so there is nothing like d-to-q. it is depended on the clock. So you have clock to q.

there will be an arc for every input to output such the input transition causes an output transition depending on the states of other pins.

Click to expand...

the timing analysis tool does not know when the latch is transparent. Does it do this d to q analysis assuming it is transparent all the time?

So such path will look like this? (c to q of launching flop -> d to q of latch -> d of capturing flop)

The critical time for a latch is when the latch goes from transparent to latched.
e.g. where E is latch signal and D is the data input
The falling edge of E latches the data on D and must meet a setup and hold time just like a flip-flop. But there is also the transparent delay from the rising clock edge to the Q output and from the D input to the Q output.

Because of these extra E-Q and D-Q paths the latch is more difficult to constrain and analyze than a flip-flop. If E is not the clock and is a enable generated from the clock you also need to create a generated clock to time the latch. Can't really help on how all these constraints should be done, as I've avoided latches since the last 3000 series FPGA design and board design (slow asynchronous bus interfaces with address latching strobe) I did a long time ago.