i.burmistrov
Newbie level 1
Hello!
I design a dual loop multiphase PLL based CDR and have some problem in phase acquisition step.
I attach some pictures, which can to help explain what is going on.
1) At the first picture shows the recovered parallel data clock signal. As you can see, some time after the start of data recovery, frequency changing about 1/10 of data rate frequency and all data recovered correctly. But at some moment frequency start to increase and at the end lock to some wrong frequency.
2) At the second picture shows the BBPD phase control output.
3) And the third picture shows BBPD internal sample clocks and input data.
I think that the reason of that is that frequency changes too fast with one BBPD control bit.
I read some books where the CDR topic was covered. In this books/articles says that CDR loop should have large damping factor to be stable (greater than one). When I calculate damping factor with formulas for BBPD CDR (this formulas I get from articles) I get that damping factor is equal to 20-50 (it is can't be true I think). So, as for stability my design should be superior, but in fact it sucks. In reality my design works better when I make resistance of LF less. I think it's wrong too.
So I just don't know how to deal with it. Maybe you can give me some directions or books/articles where I can get more info about CDR or just an advice. Many books concentrate on the jitter aspect of CDR design, but I dont much interested in jitter when system even don't work.
P.S.: article where I get furmulas of CDR stability is "Analysis of a half-rate bang-bang phase-locked-loop"
I design a dual loop multiphase PLL based CDR and have some problem in phase acquisition step.
I attach some pictures, which can to help explain what is going on.
1) At the first picture shows the recovered parallel data clock signal. As you can see, some time after the start of data recovery, frequency changing about 1/10 of data rate frequency and all data recovered correctly. But at some moment frequency start to increase and at the end lock to some wrong frequency.
2) At the second picture shows the BBPD phase control output.
3) And the third picture shows BBPD internal sample clocks and input data.
I think that the reason of that is that frequency changes too fast with one BBPD control bit.
I read some books where the CDR topic was covered. In this books/articles says that CDR loop should have large damping factor to be stable (greater than one). When I calculate damping factor with formulas for BBPD CDR (this formulas I get from articles) I get that damping factor is equal to 20-50 (it is can't be true I think). So, as for stability my design should be superior, but in fact it sucks. In reality my design works better when I make resistance of LF less. I think it's wrong too.
So I just don't know how to deal with it. Maybe you can give me some directions or books/articles where I can get more info about CDR or just an advice. Many books concentrate on the jitter aspect of CDR design, but I dont much interested in jitter when system even don't work.
P.S.: article where I get furmulas of CDR stability is "Analysis of a half-rate bang-bang phase-locked-loop"
