+ Post New Thread
Results 1 to 8 of 8
  1. #1
    Newbie level 3
    Points: 29, Level: 1

    Join Date
    May 2018
    Posts
    3
    Helped
    0 / 0
    Points
    29
    Level
    1

    Learning SystemVerilog

    Hi everybody,

    until now the only HDL language that I used was VHDL but I would like to start to learn Verilog and SystemVerilog using a suitable book. Is the relationship between Verilog and SystemVerilog same as the relationship between C and C++? If I learn SystemVerilog will I know Verilog? I am asking because of right choice among avaliable books. I wouldn't like to buy 2 books, the first about Verilog and the second about SystemVerilog, in case that the second one will teach me both of the languages.

    Thank you for your answers and sorry if my question seems a little bit stupid.

    Peter J.

    •   Alt17th May 2018, 10:59

      advertising

        
       

  2. #2
    Advanced Member level 5
    Points: 35,989, Level: 46
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,580
    Helped
    1920 / 1920
    Points
    35,989
    Level
    46

    Re: Learning SystemVerilog

    First of all, what are your reasons for learning SV? If it's purely for verification, have you had a look at the VHDL verification solutions out there? (OSVVM - my current choice, UVVM, Vunit )? SV can get very convoluted very quickly and you can do pretty much anything you need purely in VHDL. Have you attempted to do verification in VHDL?

    Secondly, Verilog no longer exists as a standard, as of 2005, it was superceded by SystemVerilog, where "oldschool" Verilog exists as part of the SystemVerilog standard (2005, 2009, 2012). SystemVerilog is really the combination of several languages mashed together, so you'll find syntax can be different for different parts of the language (Im looking at you SVA). As Ive had it described - SV is Consistently Inconstant. SystemVerilog doesnt really bring any big benefits to synthesisable code - the big benefit is verification and verification Re-Use. The big thing would be UVM.

    I didnt learn from a book - I was lucky to be sent on a Doulos course. But I already had experience with VHDL verification and Some historty with JAVA, so the OO aspect came fairly easy. Many engineers can struggle with it.



  3. #3
    Newbie level 3
    Points: 29, Level: 1

    Join Date
    May 2018
    Posts
    3
    Helped
    0 / 0
    Points
    29
    Level
    1

    Re: Learning SystemVerilog

    The main reason why I want to learn Verilog is that it is required at my diploma thesis focused on both digital design and verification. I want to learn directly SV because of benefits at verification. If I understand right learning SV will teach me the original Verilog too?



    •   Alt17th May 2018, 12:50

      advertising

        
       

  4. #4
    Advanced Member level 5
    Points: 35,989, Level: 46
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,580
    Helped
    1920 / 1920
    Points
    35,989
    Level
    46

    Re: Learning SystemVerilog

    There is no verilog any more. There is only SV. So yes, if you learn SV, you will "learn" verilog.
    Why is it a requirement to use SV? Verification can be done in any language, SV is not a magical Verification language (although many people think it is).

    Learning SV will NOT teach you verification - verification is it's own topic and the techniques can be applied to any language (although many people use SV to do it).



  5. #5
    Newbie level 3
    Points: 29, Level: 1

    Join Date
    May 2018
    Posts
    3
    Helped
    0 / 0
    Points
    29
    Level
    1

    Re: Learning SystemVerilog

    My diploma thesis will be a part of larger project. It will be focused on development of a part of software defined radio which is being developed on my university. Some components for FPGA are finished yet and are written in verilog, so the requirement of my supervisor is to use verilog too.

    By the way thank you for answers, it really helped me.



  6. #6
    Full Member level 4
    Points: 1,682, Level: 9

    Join Date
    Jul 2014
    Posts
    209
    Helped
    14 / 14
    Points
    1,682
    Level
    9

    Re: Learning SystemVerilog

    Hi,

    There is no verilog any more. There is only SV.
    why ?
    is there any recent trend in industry ?
    anyway for design we need to use only verilog right? not sv..
    dont have much knowledge in sv, os if something like above, need to learn all those uvm, etc etc things
    (i dont have much industrial knowledge , thats why i am asking)

    thanks and regrads



  7. #7
    Super Moderator
    Points: 28,821, Level: 41
    ads-ee's Avatar
    Join Date
    Sep 2013
    Location
    USA
    Posts
    6,599
    Helped
    1595 / 1595
    Points
    28,821
    Level
    41

    Re: Learning SystemVerilog

    Quote Originally Posted by dipin View Post
    Hi,


    why ?
    is there any recent trend in industry ?
    anyway for design we need to use only verilog right? not sv..
    dont have much knowledge in sv, os if something like above, need to learn all those uvm, etc etc things
    (i dont have much industrial knowledge , thats why i am asking)

    thanks and regrads
    Why because sv is the latest specification of the language. I read somewhere that the extensions to Verilog (i.e. sv) were suposed to be added to the verilog language spec not create a new one called sv. As it was ratified as sv we are now stuck with it.

    SV extensions are just that...extensions to the verilog language which is why sv is the only language now.

    There are actually quite a few enhancements that are exclusively added to improve usage for synthesis. Besides adding support for things like using arrays in ports. You should really read some of the papers on the differences, e.g. the cummings one.


    1 members found this post helpful.

    •   Alt18th May 2018, 07:50

      advertising

        
       

  8. #8
    Advanced Member level 5
    Points: 35,989, Level: 46
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,580
    Helped
    1920 / 1920
    Points
    35,989
    Level
    46

    Re: Learning SystemVerilog

    Quote Originally Posted by dipin View Post
    Hi,


    why ?
    is there any recent trend in industry ?
    anyway for design we need to use only verilog right? not sv..
    dont have much knowledge in sv, os if something like above, need to learn all those uvm, etc etc things
    (i dont have much industrial knowledge , thats why i am asking)

    thanks and regrads
    The last version of Verilog was Verilog 2005
    All versions since have been SystemVerilog - 2009, 2012 and 2017.
    SystemVerilog is a superset of Verilog, with features also taken from OpenVera and Superlog (hence the mash-up)

    Your Verilog will still work, and SystemVerilog is fully backwards compatable with old verilog. So any Verilog written in 1995 should still compile with a SV 2017 compiler.

    Generally, when people are talking about RTL, They will tend to refer to it as "Verilog", even if its written with SV constructs (such as logic type, interfaces, always_ff etc)
    When people talk about Testbenches, they will tend to refer to it as SystemVerilog.

    Also note that UVM is not a language; it is a methodology with an open source class library written in SystemVerilog.

    So when people talk about Verilog, SystemVerilog and UVM, all these people are really using the same language.


    1 members found this post helpful.

--[[ ]]--