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Learning SystemVerilog

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Peddro

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Hi everybody,

until now the only HDL language that I used was VHDL but I would like to start to learn Verilog and SystemVerilog using a suitable book. Is the relationship between Verilog and SystemVerilog same as the relationship between C and C++? If I learn SystemVerilog will I know Verilog? I am asking because of right choice among avaliable books. I wouldn't like to buy 2 books, the first about Verilog and the second about SystemVerilog, in case that the second one will teach me both of the languages.

Thank you for your answers and sorry if my question seems a little bit stupid.

Peter J.
 

First of all, what are your reasons for learning SV? If it's purely for verification, have you had a look at the VHDL verification solutions out there? (OSVVM - my current choice, UVVM, Vunit )? SV can get very convoluted very quickly and you can do pretty much anything you need purely in VHDL. Have you attempted to do verification in VHDL?

Secondly, Verilog no longer exists as a standard, as of 2005, it was superceded by SystemVerilog, where "oldschool" Verilog exists as part of the SystemVerilog standard (2005, 2009, 2012). SystemVerilog is really the combination of several languages mashed together, so you'll find syntax can be different for different parts of the language (Im looking at you SVA). As Ive had it described - SV is Consistently Inconstant. SystemVerilog doesnt really bring any big benefits to synthesisable code - the big benefit is verification and verification Re-Use. The big thing would be UVM.

I didnt learn from a book - I was lucky to be sent on a Doulos course. But I already had experience with VHDL verification and Some historty with JAVA, so the OO aspect came fairly easy. Many engineers can struggle with it.
 

The main reason why I want to learn Verilog is that it is required at my diploma thesis focused on both digital design and verification. I want to learn directly SV because of benefits at verification. If I understand right learning SV will teach me the original Verilog too?
 

There is no verilog any more. There is only SV. So yes, if you learn SV, you will "learn" verilog.
Why is it a requirement to use SV? Verification can be done in any language, SV is not a magical Verification language (although many people think it is).

Learning SV will NOT teach you verification - verification is it's own topic and the techniques can be applied to any language (although many people use SV to do it).
 

My diploma thesis will be a part of larger project. It will be focused on development of a part of software defined radio which is being developed on my university. Some components for FPGA are finished yet and are written in verilog, so the requirement of my supervisor is to use verilog too.

By the way thank you for answers, it really helped me.
 

Hi,

There is no verilog any more. There is only SV.
why ?
is there any recent trend in industry ?
anyway for design we need to use only verilog right? not sv..
dont have much knowledge in sv, os if something like above, need to learn all those uvm, etc etc things
(i dont have much industrial knowledge , thats why i am asking:shock:)

thanks and regrads
 

Hi,


why ?
is there any recent trend in industry ?
anyway for design we need to use only verilog right? not sv..
dont have much knowledge in sv, os if something like above, need to learn all those uvm, etc etc things
(i dont have much industrial knowledge , thats why i am asking:shock:)

thanks and regrads

Why because sv is the latest specification of the language. I read somewhere that the extensions to Verilog (i.e. sv) were suposed to be added to the verilog language spec not create a new one called sv. As it was ratified as sv we are now stuck with it.

SV extensions are just that...extensions to the verilog language which is why sv is the only language now.

There are actually quite a few enhancements that are exclusively added to improve usage for synthesis. Besides adding support for things like using arrays in ports. You should really read some of the papers on the differences, e.g. the cummings one.
 
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    dipin

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Hi,


why ?
is there any recent trend in industry ?
anyway for design we need to use only verilog right? not sv..
dont have much knowledge in sv, os if something like above, need to learn all those uvm, etc etc things
(i dont have much industrial knowledge , thats why i am asking:shock:)

thanks and regrads

The last version of Verilog was Verilog 2005
All versions since have been SystemVerilog - 2009, 2012 and 2017.
SystemVerilog is a superset of Verilog, with features also taken from OpenVera and Superlog (hence the mash-up)

Your Verilog will still work, and SystemVerilog is fully backwards compatable with old verilog. So any Verilog written in 1995 should still compile with a SV 2017 compiler.

Generally, when people are talking about RTL, They will tend to refer to it as "Verilog", even if its written with SV constructs (such as logic type, interfaces, always_ff etc)
When people talk about Testbenches, they will tend to refer to it as SystemVerilog.

Also note that UVM is not a language; it is a methodology with an open source class library written in SystemVerilog.

So when people talk about Verilog, SystemVerilog and UVM, all these people are really using the same language.
 
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    dipin

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Hi everybody,

until now the only HDL language that I used was VHDL but I would like to start to learn Verilog and SystemVerilog using a suitable book. Is the relationship between Verilog and SystemVerilog same as the relationship between C and C++? If I learn SystemVerilog will I know Verilog? I am asking because of right choice among avaliable books. I wouldn't like to buy 2 books, the first about Verilog and the second about SystemVerilog, in case that the second one will teach me both of the languages.

Thank you for your answers and sorry if my question seems a little bit stupid.

Peter J.

Verilog is still being used in many companies since it has been proven to be accurate in silicon, as EDA vendors change their tools to adapt SystemVerilog. So, yes SystemVerilog is becoming more popular as an HDL now since the three big vendors have synthesis tools that can convert some of the constructs into hardware. However, a majority of its features are more useful for verification.

Just like learning any language, practice is important. Its easier to learn from examples. Try https://www.chipverify.com/system-verilog/system-verilog which has quite a lot of simple examples and the corresponding outputs. They also have a detailed section on Verilog : https://www.chipverify.com/verilog/verilog-tutorial
 

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