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    Digital blocks with Verilog code

    hello
    I want to simulate a circuit in cadence include digital blocks with verilog code.
    can anyone help me?

    •   Alt15th May 2018, 17:59

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    Re: Digital blocks with Verilog code

    In cadence, that can become quite some task dependent on how well things are set up for you and your level of confidence with the tool. You would need to use, for example, the verilog-AMS simulator/netlister, which requires some extra licenses.
    My opinion might be a bit out-dated, but I think that Cadence has not really made life that simple for mixed-mode simulations. Nevertheless, check the tutorials for verilog-AMS and how to setup the tool.

    As alternatives (to be able to just use the spectre simulator):

    * If you have a moderately sized digital block: could you use verilog-A instead to describe the functional block?
    * If you have a more complex block and no feedback through analog circuits, could you simply simulate the digital blocks and output data to a file and then import that saved file into a schematic testbench through a vpwlf (or verilog-A).
    * If you are "only" simulating standard cells, and do not have too many blocks, you could implemented them with level-0 transistor models (switches). That will speed up the simulations somewhat.



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