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How to make an integrator with vcvs (ideal opamp)

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Darylpan

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How to make an integrator with vcvs(ideal opamp)

I made an ideal opamp with vcvs.But when i used this op to make an integrator sth just went wrong.Any dc voltage of input will make the output become VMAX or VMIN.Can anyone tell me why and how to solve this problem?
Thank you very much.
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And the begining of output always is the gain*(dc of input),it's wiered.The cap is uncharged at the begining so it should be 0.Why?
 

Re: How to make an integrator with vcvs(ideal opamp)

Any dc voltage of input will make the output become VMAX or VMIN
Sure that's by nature of the integrator plus your chosen analysis options. You would want to disable initial transient solution, add an initial condition or place a reset switch. In case of an ideal OP model, it would be sufficient to start with zero input voltage and delay the input signal.

Presumed you want to implement an integrator in real hardware some times, it doesn't work without a reset switch or external negative feedback.
 

Re: How to make an integrator with vcvs(ideal opamp)

Thank you for your answer.What's the reset switch,

3.png

Is this instance?where should i put it in.

OR how to add an initial condition,in the analog enviroment or the vsource? Thanks.
 

Re: How to make an integrator with vcvs(ideal opamp)

A switch across the capacitor.
 

Re: How to make an integrator with vcvs(ideal opamp)

If this is going in with other "real world" stuff you may
also want a limiting block (or strategically placed zeners)
so the thing doesn't "wind up all the way to the moon"
once the reset is released. kV makes kA makes MV makes
blow up the solution.
 

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