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    VHDL Design Verification

    What is the difference between the following VHDL Design Verifications.

    1- Pre-synthesis VHDL Design Verification
    2- Post-synthesis VHDL Design Verification
    3- Post-layout VHDL Design Verification

    The first (pre-synthesis) is very common and can be done by using ModelSim testbentch but how about the second and third ones ?

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    Re: VHDL Design Verification

    The second and third can be done in modelsim also - you're simulating a netlist against the same testbench.
    With FPGAs, people usually dont bother with 2 and 3 because they are slow and its usually just easier to finish (1) and then move directly to hardware. If you have good enough verification in 1, then assuming it met timing requirements in the compilation, then it should work. If it doesnt, you can always put chipscope/signaltap in there to find the problem.

    Usually, with good enough verification of your UUT, the errors will likely be in the interfaces around the UUT rather than in the UUT itself. This will probably come from a misinterpreted spec, or designs where "fudge factors" are needed to make things work (which should NOT be there in a well designed products - but they creep into designs when time pressures are put on products).



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    Re: VHDL Design Verification

    Thanks for reply. Regarding simulating a netlist against the same testbench which is second and third option. Do I need to run Synthesis and run Implementation in Design Tool for example Xilinx Vivado to get the required netlist which are needed to verify with testbench ?



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    Re: VHDL Design Verification

    RTL - Behavioral simulation, uses your code
    Synthesis - Gate level simulations, uses netlist generated from your code
    Implementation - Gate level simulation, uses netlist from implementation tools (may be different from synthesis due to logic replication, retiming, etc) and a SDF generated from the timing of the implemented design.

    Both gate level simulations are slow and typically unnecessary unless you are dealing with a RTL simulation synthesis mismatch problem or a tool bug.


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    Re: VHDL Design Verification

    Yes, you will need to run synthesis for a post synth netlist and implementation for a post-layout netlist.
    But why are you bothering? you'll probably spend more time getting it up and running than you could have being proper testing in stage 1 with work to test on the real hardware.

    Its only really ASIC design where (2) and (3) are more important. I think they were used more often in FPGAs in the past, but since PCs, Tools and Techniques have got better, the requirement and usefulnes of 2 and 3 has reduced (in 12 years, I havent run a single post synth or layout simulation).


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    Re: VHDL Design Verification

    Quote Originally Posted by TrickyDicky View Post
    Yes, you will need to run synthesis for a post synth netlist and implementation for a post-layout netlist.
    But why are you bothering? you'll probably spend more time getting it up and running than you could have being proper testing in stage 1 with work to test on the real hardware.

    Its only really ASIC design where (2) and (3) are more important. I think they were used more often in FPGAs in the past, but since PCs, Tools and Techniques have got better, the requirement and usefulnes of 2 and 3 has reduced (in 12 years, I havent run a single post synth or layout simulation).
    It's also less and less important for ASICs. My last design I couldn't even make the simulator load the entire netlist.
    Really, I am not Sam.


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