+ Post New Thread
Results 1 to 15 of 15
  1. #1
    Newbie level 6
    Points: 10, Level: 1

    Join Date
    Mar 2018
    Posts
    14
    Helped
    0 / 0
    Points
    10
    Level
    1

    this code for interfacing ADC 122S101 is not working

    Code Verilog - [expand]
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12
    13
    14
    15
    16
    17
    18
    19
    20
    21
    22
    23
    24
    25
    26
    27
    28
    29
    30
    31
    32
    33
    34
    35
    36
    37
    38
    39
    40
    41
    42
    43
    44
    45
    46
    47
    48
    49
    50
    51
    52
    53
    54
    55
    56
    57
    58
    59
    60
    61
    62
    63
    64
    65
    66
    67
    68
    69
    70
    71
    72
    73
    74
    75
    76
    77
    78
    79
    80
    81
    82
    83
    84
    85
    86
    87
    88
    89
    90
    91
    92
    93
    94
    95
    96
    97
    
    module adc_12b(clk,d_in,d_out,sclk,cs);
     
     input clk;     //,reset;
     input d_in;
     output [11:0] d_out;
     output sclk,cs;
     
     reg cs;
     reg [11:0] temp;
     reg [1:0] state=2'b00, nxt_state;
     reg [4:0] count,count1;
     reg [11:0] dout;
     
     assign sclk=clk;
     parameter idle=2'b00, read=2'b01;
     
     
     
    // always@(posedge clk)
    //   begin
    //       if(reset)
    //       state=idle;
    //       else
    //       state=nxt_state;
    //   end
     always@(posedge clk)
         begin
    //       if(reset)
    //       count<=0;
    //       else 
             if(count>=5'd16)
             count<=0;
             else if(state==idle)
             begin
             count<=0;
             count<=count+1;
             end
             else
             count<=0;
         end
     
     always@(posedge clk)
         begin
    //       if(reset)
    //       count1<=0;
    //       else 
             if(count1>=5'd16)
             count1<=0;
             else if(state==read)
             count1<=count1+1;
             else
             count1<=0;
         end
     
     always @(negedge clk)
         begin
             case(state)
             idle:begin
             if (count==5'd16)
                 begin
                 nxt_state <= read;
                 cs <= 1'd0;
                 end
             else
                 begin
                 nxt_state <= idle;
                 cs <= 1'd1;
                 end
             end
     
            read:begin
           if(count1<=5'd16)
                begin
                temp[0] <= d_in;
                 temp[1] <= temp[0];
                 temp[2] <= temp[1];
                 temp[3] <= temp[2];
                 temp[4] <= temp[3];
                 temp[5] <= temp[4];
                 temp[6] <= temp[5];
                 temp[7] <= temp[6];
                 temp[8] <= temp[7];
                 temp[9] <= temp[8];
                 temp[10] <= temp[9];
                 temp[11] <= temp[10];
                 nxt_state <= read;
                 end
            else
                 begin
                 nxt_state <= idle;
                 dout<=temp; 
                 end
            end
        endcase
     end
     assign d_out=dout;
     endmodule

    the timing diagram is as below

    Click image for larger version. 

Name:	Untitled123.png 
Views:	15 
Size:	41.2 KB 
ID:	146646
    Last edited by FvM; 15th May 2018 at 07:49. Reason: Added syntax tags

  2. #2
    Super Moderator
    Points: 245,634, Level: 100
    Awards:
    1st Helpful Member

    Join Date
    Jan 2008
    Location
    Bochum, Germany
    Posts
    42,668
    Helped
    13006 / 13006
    Points
    245,634
    Level
    100

    Re: this code for interfacing ADC 122S101 is not working

    Why not write a test bench and simulate the module?

    You are reading din at a reduced clock rate but operating sclk still at full rate. That can't work. You probably forgot to generate an appropriate sclk.


    1 members found this post helpful.

  3. #3
    Super Moderator
    Points: 29,149, Level: 41
    ads-ee's Avatar
    Join Date
    Sep 2013
    Location
    USA
    Posts
    6,719
    Helped
    1604 / 1604
    Points
    29,149
    Level
    41

    Re: this code for interfacing ADC 122S101 is not working

    Really you commented out the reset!?
    Why?

    FvM's suggestion to run a simulation will yield useless results as there will be X's everywhere as the FSM has no information on where to start.


    1 members found this post helpful.

    •   AltAdvertisment

        
       

  4. #4
    Newbie level 6
    Points: 10, Level: 1

    Join Date
    Mar 2018
    Posts
    14
    Helped
    0 / 0
    Points
    10
    Level
    1

    Re: this code for interfacing ADC 122S101 is not working

    Quote Originally Posted by ads-ee View Post
    Really you commented out the reset!?
    Why?

    FvM's suggestion to run a simulation will yield useless results as there will be X's everywhere as the FSM has no information on where to start.

    Could you please help me in sorting out this issue?



  5. #5
    Newbie level 6
    Points: 10, Level: 1

    Join Date
    Mar 2018
    Posts
    14
    Helped
    0 / 0
    Points
    10
    Level
    1

    Re: this code for interfacing ADC 122S101 is not working

    how to increase the clock rate simmilar to that of sclk???



  6. #6
    Advanced Member level 3
    Points: 5,356, Level: 17

    Join Date
    Feb 2015
    Posts
    887
    Helped
    256 / 256
    Points
    5,356
    Level
    17

    Re: this code for interfacing ADC 122S101 is not working

    state is used but never assigned (after initialization).

    --edit: The tragedy is that the problem nets would be among the few not shown as X!


    1 members found this post helpful.

    •   AltAdvertisment

        
       

  7. #7
    Full Member level 5
    Points: 1,994, Level: 10

    Join Date
    Nov 2013
    Location
    Germany
    Posts
    268
    Helped
    27 / 27
    Points
    1,994
    Level
    10

    Re: this code for interfacing ADC 122S101 is not working

    Quote Originally Posted by adhul View Post
    Code Verilog - [expand]
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12
    13
    14
    15
    16
    17
    18
    19
    20
    21
    22
    23
    24
    25
    26
    27
    28
    29
    30
    31
    32
    33
    34
    35
    36
    37
    38
    39
    40
    41
    42
    43
    44
    45
    46
    47
    48
    49
    50
    51
    52
    53
    54
    55
    56
    57
    58
    59
    60
    61
    62
    63
    64
    65
    66
    67
    68
    69
    70
    71
    72
    73
    74
    75
    76
    77
    78
    79
    80
    81
    82
    83
    84
    85
    86
    87
    88
    89
    90
    91
    92
    93
    94
    95
    96
    97
    
    module adc_12b(clk,d_in,d_out,sclk,cs);
     
     input clk;     //,reset;
     input d_in;
     output [11:0] d_out;
     output sclk,cs;
     
     reg cs;
     reg [11:0] temp;
     reg [1:0] state=2'b00, nxt_state;
     reg [4:0] count,count1;
     reg [11:0] dout;
     
     assign sclk=clk;
     parameter idle=2'b00, read=2'b01;
     
     
     
    // always@(posedge clk)
    //   begin
    //       if(reset)
    //       state=idle;
    //       else
    //       state=nxt_state;
    //   end
     always@(posedge clk)
         begin
    //       if(reset)
    //       count<=0;
    //       else 
             if(count>=5'd16)
             count<=0;
             else if(state==idle)
             begin
             count<=0;
             count<=count+1;
             end
             else
             count<=0;
         end
     
     always@(posedge clk)
         begin
    //       if(reset)
    //       count1<=0;
    //       else 
             if(count1>=5'd16)
             count1<=0;
             else if(state==read)
             count1<=count1+1;
             else
             count1<=0;
         end
     
     always @(negedge clk)
         begin
             case(state)
             idle:begin
             if (count==5'd16)
                 begin
                 nxt_state <= read;
                 cs <= 1'd0;
                 end
             else
                 begin
                 nxt_state <= idle;
                 cs <= 1'd1;
                 end
             end
     
            read:begin
           if(count1<=5'd16)
                begin
                temp[0] <= d_in;
                 temp[1] <= temp[0];
                 temp[2] <= temp[1];
                 temp[3] <= temp[2];
                 temp[4] <= temp[3];
                 temp[5] <= temp[4];
                 temp[6] <= temp[5];
                 temp[7] <= temp[6];
                 temp[8] <= temp[7];
                 temp[9] <= temp[8];
                 temp[10] <= temp[9];
                 temp[11] <= temp[10];
                 nxt_state <= read;
                 end
            else
                 begin
                 nxt_state <= idle;
                 dout<=temp; 
                 end
            end
        endcase
     end
     assign d_out=dout;
     endmodule

    the timing diagram is as below

    Click image for larger version. 

Name:	Untitled123.png 
Views:	15 
Size:	41.2 KB 
ID:	146646
    I suggest you do not use nxt_state and assign the state signal to idle or read parameters. If you are planning to then u need to define it properly so that it shifts from state to nxt_state or you can simply write state instead of nxt_state.

    1. Instead of using nxt_state use state = idle/read in your code above.
    2. You also need to assign if(count1<5'd16) to get your temp value assigned to dout otherwise you do not get any output.

    As the other guys mentioned use a test bench to fine tune your code. You just need 2 input signals in your test bench. Are you sure that the din input is just 1 bit?

    - - - Updated - - -

    Quote Originally Posted by ads-ee View Post
    Really you commented out the reset!?
    Why?

    FvM's suggestion to run a simulation will yield useless results as there will be X's everywhere as the FSM has no information on where to start.
    Reset is commented because for the obvious reason that its not at all used in the module. It should work without reset.


    1 members found this post helpful.

    •   AltAdvertisment

        
       

  8. #8
    Newbie level 6
    Points: 10, Level: 1

    Join Date
    Mar 2018
    Posts
    14
    Helped
    0 / 0
    Points
    10
    Level
    1

    Re: this code for interfacing ADC 122S101 is not working

    thank you sir.. the code get synthesized.. but when i tried to put it on spartan 6 and the output was observed by varying the potentiometer the last msb bits are not coming and also if the input voltage to the ADC is 3.3V then by 1.7V the 10 leds glows,which means the output is wrong . what the error can be??
    i have been doing that but nothing is happening my way..
    The code is attached below

    Code Verilog - [expand]
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12
    13
    14
    15
    16
    17
    18
    19
    20
    21
    22
    23
    24
    25
    26
    27
    28
    29
    30
    31
    32
    33
    34
    35
    36
    37
    38
    39
    40
    41
    42
    43
    44
    45
    46
    47
    48
    49
    50
    51
    52
    53
    54
    55
    56
    57
    58
    59
    60
    61
    62
    63
    64
    65
    66
    67
    68
    69
    70
    71
    72
    73
    74
    75
    76
    77
    78
    79
    80
    81
    82
    83
    84
    85
    86
    87
    88
    89
    90
    91
    92
    93
    94
    95
    96
    97
    98
    99
    100
    101
    102
    103
    
    module adc_new1(clk,d_in,,ch,d_out,sclk,cs);
     
     input clk;     
     input d_in;
     output ch;
     output [15:0] d_out;
     output sclk,cs;
     
     wire cs;
     reg [15:0] temp;
     reg [1:0] state=2'b00;
     reg [4:0] count=0;
     reg [4:0]count1=0;
     reg [15:0] dout;
     reg ch=0;
     assign sclk=clk;
     parameter idle=2'b00, read=2'b01;
     assign cs = 1'd0;
     
     
    // always@(posedge clk)
    //   begin
    //       if(reset)
    //       state=idle;
    //       else
    //       state=nxt_state;
    //   end
     always@(posedge clk)
         begin
    //       if(reset)
    //       count<=0;
    //       else 
             if(count>5'd3)
             count<=0;
             else if(state==idle)
             begin
             //count<=0;
             count<=count+1;
             end
             else
             count<=0;
         end
     
     always@(posedge clk)
         begin
    //       if(reset)
    //       count1<=0;
    //       else 
             if(count1>5'd15)
             count1<=0;
             else if(state==read)
             count1<=count1+1;
             else
             count1<=0;
         end
     
     always @(posedge clk)
         begin
             case(state)          
             idle:begin
             if (count==5'd15)
                 begin
                 state <= read;
                 //cs <= 1'd0;
                 end
             else 
                 begin
                 state <= idle;
                 //cs <= 1'd1;
                 end
             end
     
            read:begin
           if(count1<=5'd15)
                begin
                temp[0] <= d_in;
                 temp[1] <= temp[0];
                 temp[2] <= temp[1];
                 temp[3] <= temp[2];
                 temp[4] <= temp[3];
                 temp[5] <= temp[4];
                 temp[6] <= temp[5];
                 temp[7] <= temp[6];
                 temp[8] <= temp[7];
                 temp[9] <= temp[8];
                 temp[10] <= temp[9];
                 temp[11] <= temp[10];
                     temp[12] <= temp[11];
                     temp[13] <= temp[12];
                     temp[14] <= temp[13];
                     temp[15] <= temp[14];
                 state <= read;
                 end
            else
                 begin
                 state <= idle;
                 dout<=temp; 
                 end
            end
        endcase
     end
     assign d_out=dout;
     endmodule
    Last edited by BradtheRad; 31st May 2018 at 03:12. Reason: Added code formatted window



  9. #9
    Super Moderator
    Points: 245,634, Level: 100
    Awards:
    1st Helpful Member

    Join Date
    Jan 2008
    Location
    Bochum, Germany
    Posts
    42,668
    Helped
    13006 / 13006
    Points
    245,634
    Level
    100

    Re: this code for interfacing ADC 122S101 is not working

    CS is not operated in the latest code, can't work.

    - - - Updated - - -

    Additional points, you never mentioned the clock frequency driving your design. Consider that ADC122S101 must keep an SCLK range of 8 to 16 MHz. I see that you have been playing around with clock edges. It's correct to read DOUT at the rising edge of SCLK, to comply with the datasheet specification, CS (and also DIN, if utilized) must be set at the falling SCLK edge.

    The best way to achieve it is to clock the design at double SCLK frequency and toggle SCLK in your design.


    1 members found this post helpful.

  10. #10
    Newbie level 6
    Points: 10, Level: 1

    Join Date
    Mar 2018
    Posts
    14
    Helped
    0 / 0
    Points
    10
    Level
    1

    Re: this code for interfacing ADC 122S101 is not working

    Quote Originally Posted by FvM View Post
    CS is not operated in the latest code, can't work.

    - - - Updated - - -

    Additional points, you never mentioned the clock frequency driving your design. Consider that ADC122S101 must keep an SCLK range of 8 to 16 MHz. I see that you have been playing around with clock edges. It's correct to read DOUT at the rising edge of SCLK, to comply with the datasheet specification, CS (and also DIN, if utilized) must be set at the falling SCLK edge.

    The best way to achieve it is to clock the design at double SCLK frequency and toggle SCLK in your design.
    K







    Sir,
    Sorry i put the wrong code this was the code


    Code:
    module adc_new1(clk,d_in,,ch,d_out,sclk,cs);
     
     input clk;     
     input d_in;
     output ch;
     output [11:0] d_out;
     output sclk,cs;
     
     reg cs;
     reg [11:0] temp;
     reg [1:0] state=2'b00;
     reg [4:0] count=0,count1=0;
     reg [11:0] dout;
     reg ch=0;
     assign sclk=clk;
     parameter idle=2'b00, read=2'b01;
     
     
     
    // always@(posedge clk)
    //   begin
    //       if(reset)
    //       state=idle;
    //       else
    //       state=nxt_state;
    //   end
     always@(posedge clk)
         begin
    //       if(reset)
    //       count<=0;
    //       else 
             if(count>=5'd16)
             count<=0;
             else if(state==idle)
             begin
             count<=0;
             count<=count+1;
             end
             else
             count<=0;
         end
     
     always@(posedge clk)
         begin
    //       if(reset)
    //       count1<=0;
    //       else 
             if(count1>=5'd16)
             count1<=0;
             else if(state==read)
             count1<=count1+1;
             else
             count1<=0;
         end
     
     always @(negedge clk)
         begin
             case(state)          
             idle:begin
             if (count==5'd16)
                 begin
                 state <= read;
                 cs <= 1'd0;
                 end
             else 
                 begin
                 state <= idle;
                 cs <= 1'd1;
                 end
             end
     
            read:begin
           if(count1<5'd16)
                begin
                temp[0] <= d_in;
                 temp[1] <= temp[0];
                 temp[2] <= temp[1];
                 temp[3] <= temp[2];
                 temp[4] <= temp[3];
                 temp[5] <= temp[4];
                 temp[6] <= temp[5];
                 temp[7] <= temp[6];
                 temp[8] <= temp[7];
                 temp[9] <= temp[8];
                 temp[10] <= temp[9];
                 temp[11] <= temp[10];
                 state <= read;
                 end
            else
                 begin
                 state <= idle;
                 dout<=temp; 
                 end
            end
        endcase
     end
     assign d_out=dout;
     endmodule
    Last edited by KlausST; 31st May 2018 at 10:08. Reason: added code tags



  11. #11
    Super Moderator
    Points: 245,634, Level: 100
    Awards:
    1st Helpful Member

    Join Date
    Jan 2008
    Location
    Bochum, Germany
    Posts
    42,668
    Helped
    13006 / 13006
    Points
    245,634
    Level
    100

    Re: this code for interfacing ADC 122S101 is not working

    Now reading d_in at the wrong SCLK edge.


    1 members found this post helpful.

    •   AltAdvertisment

        
       

  12. #12
    Newbie level 6
    Points: 10, Level: 1

    Join Date
    Mar 2018
    Posts
    14
    Helped
    0 / 0
    Points
    10
    Level
    1

    Re: this code for interfacing ADC 122S101 is not working

    "The best way to achieve it is to clock the design at double SCLK frequency and toggle SCLK in your design."

    how to code this ???



  13. #13
    Full Member level 5
    Points: 1,994, Level: 10

    Join Date
    Nov 2013
    Location
    Germany
    Posts
    268
    Helped
    27 / 27
    Points
    1,994
    Level
    10

    Re: this code for interfacing ADC 122S101 is not working

    Can you tell the clk and sclk value? In the pic share above in your first post, is the waveform of your clk and sclk signal the same? There is missing information of your clk in the timing diagram, can you repost the timing diagram with clk signal in it?


    1 members found this post helpful.

  14. #14
    Newbie level 6
    Points: 10, Level: 1

    Join Date
    Mar 2018
    Posts
    14
    Helped
    0 / 0
    Points
    10
    Level
    1

    Re: this code for interfacing ADC 122S101 is not working

    thanks for you reply.
    In the timing diagram also they didnt mentioned about the clock frequency.
    i assumed it to be the same and followed the remaining.

    i got the output also. initially i put the frequency as 20 MHz but some bits was missing but later i changed to frequency of about 4 MHz. So i got the output.



  15. #15
    Super Moderator
    Points: 61,824, Level: 60
    Achievements:
    7 years registered
    Awards:
    Most Frequent Poster 3rd Helpful Member

    Join Date
    Apr 2014
    Posts
    12,597
    Helped
    2921 / 2921
    Points
    61,824
    Level
    60

    Re: this code for interfacing ADC 122S101 is not working

    Hi,

    In the timing diagram also they didnt mentioned about the clock frequency.
    clk: is only in the FPGA, thus it is not meantioned in the datasheet
    sclk: for sure is specified in the datasheet: 8MHz <= F_sclk <= 16MHz.
    --> 20MHz is out of specification.

    Please read the datsheet.

    Klaus
    Please don´t contact me via PM, because there is no time to respond to them. No friend requests. Thank you.



--[[ ]]--