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  1. #1
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    this code for interfacing ADC 122S101 is not working

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    module adc_12b(clk,d_in,d_out,sclk,cs);
     
     input clk;     //,reset;
     input d_in;
     output [11:0] d_out;
     output sclk,cs;
     
     reg cs;
     reg [11:0] temp;
     reg [1:0] state=2'b00, nxt_state;
     reg [4:0] count,count1;
     reg [11:0] dout;
     
     assign sclk=clk;
     parameter idle=2'b00, read=2'b01;
     
     
     
    // always@(posedge clk)
    //   begin
    //       if(reset)
    //       state=idle;
    //       else
    //       state=nxt_state;
    //   end
     always@(posedge clk)
         begin
    //       if(reset)
    //       count<=0;
    //       else 
             if(count>=5'd16)
             count<=0;
             else if(state==idle)
             begin
             count<=0;
             count<=count+1;
             end
             else
             count<=0;
         end
     
     always@(posedge clk)
         begin
    //       if(reset)
    //       count1<=0;
    //       else 
             if(count1>=5'd16)
             count1<=0;
             else if(state==read)
             count1<=count1+1;
             else
             count1<=0;
         end
     
     always @(negedge clk)
         begin
             case(state)
             idle:begin
             if (count==5'd16)
                 begin
                 nxt_state <= read;
                 cs <= 1'd0;
                 end
             else
                 begin
                 nxt_state <= idle;
                 cs <= 1'd1;
                 end
             end
     
            read:begin
           if(count1<=5'd16)
                begin
                temp[0] <= d_in;
                 temp[1] <= temp[0];
                 temp[2] <= temp[1];
                 temp[3] <= temp[2];
                 temp[4] <= temp[3];
                 temp[5] <= temp[4];
                 temp[6] <= temp[5];
                 temp[7] <= temp[6];
                 temp[8] <= temp[7];
                 temp[9] <= temp[8];
                 temp[10] <= temp[9];
                 temp[11] <= temp[10];
                 nxt_state <= read;
                 end
            else
                 begin
                 nxt_state <= idle;
                 dout<=temp; 
                 end
            end
        endcase
     end
     assign d_out=dout;
     endmodule

    the timing diagram is as below

    Click image for larger version. 

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    Last edited by FvM; 15th May 2018 at 07:49. Reason: Added syntax tags

    •   Alt15th May 2018, 07:44

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  2. #2
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    Re: this code for interfacing ADC 122S101 is not working

    Why not write a test bench and simulate the module?

    You are reading din at a reduced clock rate but operating sclk still at full rate. That can't work. You probably forgot to generate an appropriate sclk.



    •   Alt15th May 2018, 07:53

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  3. #3
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    Re: this code for interfacing ADC 122S101 is not working

    Really you commented out the reset!?
    Why?

    FvM's suggestion to run a simulation will yield useless results as there will be X's everywhere as the FSM has no information on where to start.


    1 members found this post helpful.

    •   Alt15th May 2018, 19:07

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  4. #4
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    Re: this code for interfacing ADC 122S101 is not working

    Quote Originally Posted by ads-ee View Post
    Really you commented out the reset!?
    Why?

    FvM's suggestion to run a simulation will yield useless results as there will be X's everywhere as the FSM has no information on where to start.

    Could you please help me in sorting out this issue?



  5. #5
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    Re: this code for interfacing ADC 122S101 is not working

    how to increase the clock rate simmilar to that of sclk???



    •   Alt16th May 2018, 03:21

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  6. #6
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    Re: this code for interfacing ADC 122S101 is not working

    state is used but never assigned (after initialization).

    --edit: The tragedy is that the problem nets would be among the few not shown as X!



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