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RTL for linear search

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sky_above

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RTL for binary search

Can you please write a RTL which can do binary search on an input number of any width to search the position of that number in a memory where numbers are stored?
 
Last edited:

Hi,

you want someone to do your homework?

I assume there are informations missing, like: File format, how the numbers are stored, how the nubers are separated...
"of any width" is a bit vague...

Klaus
 

KlausST said:
Hi,

you want someone to do your homework?

I assume there are informations missing, like: File format, how the numbers are stored, how the nubers are separated...
"of any width" is a bit vague...

Klaus
Click to expand...

A RTL is wanted for the following block where the block has an input and an output. The block has a memory where numbers can be stored. At the input a number can come and the position of that number in the memory should be told by the output of the block by binary search algorithm. Can you please provide a RTL?

KlausST said:
Hi,
I assume there are informations missing, like: File format, how the numbers are stored, how the nubers are separated...
"of any width" is a bit vague...
Klaus
Click to expand...

You can assume a width. File format will be verilog file format. Numbers are strored as in a SRAM or other memories.
 

No one is doing your homework. You have the specs, what is stopping you from doing it? This is a rather simple algorithm.
 

ThisIsNotSam said:
No one is doing your homework. You have the specs, what is stopping you from doing it? This is a rather simple algorithm.
Click to expand...

This is not home work. Can you please provide the rtl?
 

Can you please provide the rtl?
Click to expand...
I am pretty much sure no one will provide.

But.............if you have tried writing the RTL and have problems, then that can be helped!
 

sky_above said:
This is not home work. Can you please provide the rtl?
Click to expand...

You are entirely missing the point. Edaboard is not a free consulting web site to get someone to do your JOB for you.

If you are not capable of doing this task you should go to your manager and tell them you are not capable of doing this job and need help.

If you are learning on your own, then read, read, read, read, read, read, learn, learn, learn, learn, do, do, do, do, ....then ask specific question on what you don't understand. Don't just ask someone to write your code for you, that just makes you look lazy and not worth anyone's time to help.
 

sky_above said:
This is not home work. Can you please provide the rtl?
Click to expand...

If this is not homework, then what is it? This is not the type of question an engineer would ask, even if you were the junior most employee of the company.
 

ThisIsNotSam said:
If this is not homework, then what is it? This is not the type of question an engineer would ask, even if you were the junior most employee of the company.
Click to expand...

You're assuming they graduated from a university that actually cares about graduating students that know something. I've interviewed (final year) interns with no grasp of ohms law, not exactly sure how they got into a US university master's program.
 

dpaul said:
I am pretty much sure no one will provide.

But.............if you have tried writing the RTL and have problems, then that can be helped!
Click to expand...

Can anybody please see while the following rtl will be synthesizable or not and while this rtl can do the binary search or not ? This will synthesize to combinational blocks only. There is no simulator/synthesis tool here. Can anybody please do a syntax check in a synthesis tool to check it synthesizability and syntax issues?

Code Verilog - [expand]
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module (m,ou);
 
parameter n=6;
parameter d=8;
input [n-1 : 0] m;
ouput [n-1 : 0] ou;
reg [n-1 : 0] ou;
reg [d-1,0]stor[n-1, 0];
integer i,s,t;
 
assign s=0;
assign t=(n-1)/2;
 
always @(m)
 
for (i=0, i<=n/2 , i++)
 
if (m < mem[(s+n)/2])
 
n= (s+n)/2 -1;
 
else if ( m > mem[(s+n)/2])
 
s= (s+n)/2 -1;
 
else
ou = (s+n)/2 ;
i=n\2;
 
endmodule



Will the following code also do the binary search and will be synthesizable? It will synthesize to sequential logic. There is no simulator/synthesis tool here. Can anybody please do a syntax check in a synthesis tool to check it synthesizability and syntax issues?

Code Verilog - [expand]
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module (m,ou, clk, rest);
 
parameter n=6;
parameter d=8;
 
input [n-1 : 0] m;
input clk, rest;
ouput [n-1 : 0] ou;
reg [n-1 : 0] ou;
reg [d-1,0]stor[n-1, 0];
integer i,s,t;
 
assign s=0;
assign t=(n-1)/2;
 
while (i <n\2)
 
always @(posedgle clk or negedge rest)
 
if (rest == 1'b0)
 
ou <= 0;
 
else
 
if (m < mem[(s+n)/2])
 
n= (s+n)/2 -1;
 
else if ( m > mem[(s+n)/2])
 
s= (s+n)/2 -1;
 
else
ou = (s+n)/2 ;
i=n\2;
 
endmodule
 
Last edited:

sky_above said:
Can you please see while the following rtl will be synthesizable
Click to expand...

This code would not even be compilable since there is a syntax error. I leave it to you to find out, or at least to compile (which is the minimum effort expected of you).
 

andre_teprom said:
This code would not even be compilable since there is a syntax error. I leave it to you to find out, or at least to compile (which is the minimum effort expected of you).
Click to expand...

As I wrote there is no tool here even not a compiler. If there was a compiler, then definitely it would have been compiled before posting here.

Regards

- - - Updated - - -

Can anybody name a good book where RTL s are written from algorithms including the algorithm for binary search?
 

sky_above said:
As I wrote there is no tool here even not a compiler. If there was a compiler, then definitely it would have been compiled before posting here.
Click to expand...

So you are doing the things in the wrong order; First be prepared with the tools you need, then review the available examples and online language tutorials, and then make experiments by yourself, and finally get help if the previous steps were not enough to help you.
 

andre_teprom said:
So you are doing the things in the wrong order; First be prepared with the tools you need, then review the available examples and online language tutorials, and then make experiments by yourself, and finally get help if the previous steps were not enough to help you.
Click to expand...

Not possible to get tools now.
 

Not possible to get tools now.
Click to expand...

I'm afraid to ask why, but I'm sure that as soon as you can get them, people will be glad to help you as long you bring the posts with real issues rather bare requests; read above posts, you were already warned on how things works on forums.
 

ThisIsNotSam said:
Go play with FPGAs then. Tools are not a problem.
Click to expand...

That is also not possible.


No proper solution is obtained till now from anybody for the code. Can anybody comment whether the code is right or not ? Small mistakes like module name missing , ; present can be ignored,but please state the major problems in this code if any.

Can anybody suggest the name of a good book where examples to write RTLs for different algorithms are taught ?
 

Can anybody comment whether the code is right or not ?
Click to expand...
A good start would be to look at the syntaxhighlighter itself in the code you posted above, and see that there is a blatant error. I still let this task for you.

That is also not possible.
Click to expand...

As for the impediment to use any tool, as a sign of commitment on your side, one would expect to hear you explain why, but whatever; There are online tools with which you could evaluate your code, and in the course of that time would be to suppose that you had already looked for them, if not, follow one of them, have fun:

https://www.edaplayground.com/

Can anybody suggest the name of a good book
Click to expand...

Each one has his preference, and currently there is nothing better than online tutorials, being this one perhaps the most recommended for beginners:

https://www.asic-world.com/verilog/index.html

But if you insist on a printed version, there make a search on the free to use PDFs available by universitie's websites which are very detailed and suited for those who want to take the fundamentals.

No proper solution is obtained till now from anybody for the code
Click to expand...

However, if you still expect someone to compile and make tests with the above code for you, this would be a sign of little effort on your part, a strong demotivator for giving you any help.
 

I think it is time to close this topic. OP is clearly looking for someone to do his job.
 

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