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  1. #1
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    Unknown Clock Signal

    Hi,
    In my simple design, I am giving some inputs and it is difficult for me to know which signal act as a clock. i.e. only "y" act as a clock or both "x" and "y" act as clock.

    Code:
    module my_design (q, d, x, y);
    input x, y, d;
    output reg q;
    
    always@(posedge x or posedge y)
    begin
     if(x)
    q <= 1'b0;
    else
     q <= d;
    end
    endmodule
    Last edited by KlausST; 14th May 2018 at 07:26. Reason: added code tags

    •   Alt14th May 2018, 07:13

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  2. #2
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    Re: Unknown Clock Signal

    Hi,

    input x, y, clk;
    Maybe I didn't understant your question correctly.

    There are three inputs:
    * x
    * y
    * clk

    Obviously "clk" is the clock input.

    Klaus
    Please don´t contact me via PM, because there is no time to respond to them. Thank you.



    •   Alt14th May 2018, 07:24

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  3. #3
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    Re: Unknown Clock Signal

    Ohhh right Klaus,
    I have edited that.



    •   Alt14th May 2018, 07:27

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    Re: Unknown Clock Signal

    Despite of the event specification "posedge x", x is acting as level sensitive input in this well know Verilog template for a DFF with asynchronous reset.

    A detailed explanation can be found in the (withdrawn) IEEE Std 1364.1 Verilog Register Transfer Level Synthesis

    Click image for larger version. 

Name:	DFF with reset.png 
Views:	6 
Size:	459.3 KB 
ID:	146623


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  5. #5
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    Re: Unknown Clock Signal

    Quote Originally Posted by FvM View Post
    Despite of the event specification "posedge x", x is acting as level sensitive input in this well know Verilog template for a DFF with asynchronous reset.

    A detailed explanation can be found in the (withdrawn) IEEE Std 1364.1 Verilog Register Transfer Level Synthesis

    Click image for larger version. 

Name:	DFF with reset.png 
Views:	6 
Size:	459.3 KB 
ID:	146623
    After reading this I understood the actual meaning of that always statement, Thanks, guys............



    Sandy.



    •   Alt14th May 2018, 10:02

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  6. #6
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    Re: Unknown Clock Signal

    This is one of the minor things I don't like about Verilog. In VHDL, you can have registers without reset in the same process as registers with reset. The reset logic just is placed at the end of the process.



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