Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Why higherk frequency circuit may encounter hold time violation for low frequency?

Status
Not open for further replies.

Anklon

Member level 1
Joined
Dec 1, 2013
Messages
32
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
310
If I design a circuit for high frequency clock (suppose 9MHz ) , handle all setup and hold type violation it will work fine 9MHz.
As low frequency will provide greater clock period , that high frequency circuit should work fine.
I encountered with some online resources where it mention, In this case, the circuit may encounter with hold time violation. Can you please explain me why would it encounter hold violation ?
Is it obvious that it will encounter this violation or may be it may encounter this violation.
 

It could be effect if crossing clock domain.

- - - Updated - - -

It could be effect if crossing clock domain.

Sorry, my mistake . It could be encountered with half cycle.
 

Could you please explain it ?
Why encounter with half cycle will cause hold time violation as its equation do not related to system clock directly ? An example would be nice.
 

Example we have some delay variable : FF0 (pos-edge ) -> FF1 (neg-edge) , T = peirod of CK
T_launch : CK -> FF0/CLK
T_comp : FF0/Q -> FF1/D
T_cap : CK -> FF1/CLK

Hold time check requirement :
T_launch + T_comp > T_cap + T/2 + T_hold

If the clock period expand , T/2 will effect the hold check.
 

It could be effect if crossing clock domain.

- - - Updated - - -



Sorry, my mistake . It could be encountered with half cycle.

this has nothing to do with CDC, it has to do with the low frequency propagation of the clock on the clock tree being slightly different than when the clock frequency is high.


OP, this problem is almost a clock simulation problem. when the clock is "high frequency", the clock tree will be designed such that every leaf receives the clock signal while respecting setup and hold.
however, when the clock is changed to "low frequency", it might propagate in a slightly different way. say you have one clock branch that is heavily buffered, vs one that was on the edge of the min buffering necessary. a small change in clock frequency then becomes a small change in clock slew that becomes a small change in crosstalk between wires that sees a small difference in process variation... and on and on and on.

My point is that for every frequency the system is supposed to operate at, you have to close setup and hold timing for it. You cannot assume because it works for high frequency it will keep working for low.
 
  • Like
Reactions: Anklon

    Anklon

    Points: 2
    Helpful Answer Positive Rating
For my project , my professor demanded that we use internal clock (no external reference or source clock) . And I did. But as it is internal , it changes from ff_corner to ss_corner.The changes is around 20% .Now I'm looking for a solution where I could synthesize the circuit which could maintain this range.From you explanation , I can say that ensuring such situation is not possible ?

Is there any way (like including this change as setup and hold uncertainty ) to handle this ?
If there is no other way, I have to solve the violations for a particular frequency. Then which frequency would be the safest bet ? tt_frequency (9MHz) or ff_frequency ( 11MHz) or ss_frequency (6.5MHz) ?
SideNote: As my professor demanded to include this clock inside the circuit, I could not use other clock here. It's kind of my design's requirement.

Thank you for your time :)
 

My point is that for every frequency the system is supposed to operate at, you have to close setup and hold timing for it. You cannot assume because it works for high frequency it will keep working for low.

I would expect a rugged design to meet timing from 0 up to a maximum clock frequency. Presuming the explanation about frequency dependent clock skew is correct, shouldn't we reconsider the topology?
 

I would expect a rugged design to meet timing from 0 up to a maximum clock frequency. Presuming the explanation about frequency dependent clock skew is correct, shouldn't we reconsider the topology?

The clock tree should be aware of all the process corners and functional corners, such that it will be built to respect timing in all cases. Physical synthesis tools will take care of everything under the hood as long as you specify your corners correctly.

- - - Updated - - -

For my project , my professor demanded that we use internal clock (no external reference or source clock) . And I did. But as it is internal , it changes from ff_corner to ss_corner.The changes is around 20% .Now I'm looking for a solution where I could synthesize the circuit which could maintain this range.From you explanation , I can say that ensuring such situation is not possible ?

Is there any way (like including this change as setup and hold uncertainty ) to handle this ?
If there is no other way, I have to solve the violations for a particular frequency. Then which frequency would be the safest bet ? tt_frequency (9MHz) or ff_frequency ( 11MHz) or ss_frequency (6.5MHz) ?
SideNote: As my professor demanded to include this clock inside the circuit, I could not use other clock here. It's kind of my design's requirement.

Thank you for your time :)

I assume you have one .lib file for each process corner. Just build your MMMC file such that the right .lib is matched with the right corner and you will be fine.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top