Anklon
Member level 1
If I design a circuit for high frequency clock (suppose 9MHz ) , handle all setup and hold type violation it will work fine 9MHz.
As low frequency will provide greater clock period , that high frequency circuit should work fine.
I encountered with some online resources where it mention, In this case, the circuit may encounter with hold time violation. Can you please explain me why would it encounter hold violation ?
Is it obvious that it will encounter this violation or may be it may encounter this violation.
As low frequency will provide greater clock period , that high frequency circuit should work fine.
I encountered with some online resources where it mention, In this case, the circuit may encounter with hold time violation. Can you please explain me why would it encounter hold violation ?
Is it obvious that it will encounter this violation or may be it may encounter this violation.