[SOLVED] Comparator-based OCP shutdown only limiting, not shutting down.

Hi,

The circuit shown is intended to make U2 high when current is below 124mA and U2 should be low when the current is over 124mA. I have simulated a multitude of options, none work correctly in simulations nor do the ones I breadboarded to be sure reality matched simulation. Nor does disconnecting LED strings and only having a 10R resistor as a load (real world, not simulation)



The LM193 comparator is definitely within it's common-mode range (INA214 is 100V/V amplification. 100milliOhm * 0.125A = 1.25V; Vref = 1.24V).

Instead of switching the U2 NMOS off, it just goes into current-limiting mode: The Vleds test point voltage falls with rising current and the housekeeping current rises in inverse direction. e.g. for 2 strings with 5R sensing resistors (not the 49.6R they should all be), Vleds drops to ~3.9V and AM1 rises to ~180mA, so housekeeping rises from 2 to 3mA to ~60mA - disastrous waste of finite energy for a battery circuit.

The comparator won't fall to 0V, it drops to ~3V when it is sinking. It has to turn off fully so U2 fully turns off - that is the intention.

I have tried placing a CMOS AND gate between comparator and U2; bipolar and MOS push-pull stages; various other transistor buffers; a comparator after the U3 one with ref level 7V to detect a divided down < 12V, switch to sinking and in this way pull U2 fully to ground.

I feel I can't see the wood for the trees and the problem is something I should understand by now and may be related to the "load" at the MOSFET output affecting how low U3 can sink but I just can't see or find the cause or how to achieve intended functioning.

Why is this happening: "excellent" unintended current limiting but no intended current shutdown?

Thanks.

The current limiting behavior is by design, most likely oscillating due to missing control amplifier compensation. To achieve shutdown, you need a latch that keeps the pass transistor off after being triggered once. Possible problem is trigger by inrush current, so you may need a time filter.

If you want latched overcurrent protection then there
had better be a latch (SRFF) in the lineup somewhere.
I see none, so the mode is probably comparator chatter
(motorboating, similar to UVLO behaviors) which after
the filter looks like something continuous.

Which the user prefers, is a question. Needing to power-
cycle after every momentary current spike is not well
received in some circles.

The circuit is configured as a current-limiter and that's how it is functioning.
If you want the output to latch off after an overload then you need to add a latch.

Note that an N-MOSFET is acting as a source-follower to limit the current, which means the output will never be higher than the MOSFET Vgs(th) below the input.
If you want the output voltage to be equal to the input, a P-MOSFET should be used.
That will reverse the polarity of the current limit signal.

Hi,

Thanks. I hadn't known that. I thought an op amp would modulate the current via a pass device and a current limit comparator would switch a pass device on and off.

I made a silly but understandable simulating mistake. I had been labouring under the notion that it was a steady-state circuit: I'd expected that it would be on or off so I only simulated it that way (where all the voltages and currents appear, no waveforms). Earlier this afternoon I tried a 1-second transient by chance and the waveforms show it is going into what I think is hiccup mode on a 12V supply. Maybe that was just the comparator oscillating, as was suggested. It doesn't hiccup/oscillate if the input voltage is 9V, then it does only current limit - I guess that could be due to lack the of operating headroom to provide the power needed? A mediocre circuit, I surmise. I'll upload the 12V overcurrent voltage and current waveforms - they rise "slowly" and fall instantly, are off a while then repeat the slow rising fast falling pattern, etc.

I also should have said that a time delay circuit of some kind between comparator and the pass device was the eventual goal after getting this part to function correctly. I spent all day simulating and breadboarding this yesterday and have lost significant brain capacity in the process so I didn't mention that important point earlier.

Seeing the benefit of a PMOS, I'll try again with a fairly-matched substitute to the NMOS, thanks.

Would this benefit from a soft start circuit as there may be current spikes? The simulation shows none for normal operation and something brief from 250mA to 400 - 500mA then quickly back to 124mA.

**broken link removed** **broken link removed**

You didn't yet state clearly what's the intended circuit operation. If it's hiccup current limit, you should tell the parameters. If it's permanent shutdown, there must be a bistable circuit and a reset means, e.g. by cycling the power.

FvM said:

You didn't yet state clearly what's the intended circuit operation. If it's hiccup current limit, you should tell the parameters. If it's permanent shutdown, there must be a bistable circuit and a reset means, e.g. by cycling the power.

Click to expand...

Hi,

I may not have read enough on this subject. I had thought from what I understood that with a comparator, a voltage reference, a current shunt monitor and a sensing resistor it would be possible to control the gate of a pass device fully on or fully off. By extension, a timeout device or a latch to shutdown can be added between the comparator and the pass device to force the faulty circuit into shutdown and not hiccup mode.

Idea is:
Led current total: 100mA = Pass device on and LED strings and LED drive circuitry on.
Led current total: >124mA = Pass device off and LED strings and LED drive circuitry off.
The intended circuit operation is ultimately permanent shutdown. If the current rises above 124mA the LEDs and their drive circuitry should shut down (so as to not waste battery power which it does in current limiting).

Do these waveforms basically have the correct shape for hiccup mode when there is an overcurrent condition, please? I think so but I've never seen it so I want to check with an adult:



What did you mean by parameters for hiccup mode?

Thanks.

- - - Updated - - -

crutschow said:

The circuit is configured as a current-limiter and that's how it is functioning.
If you want the output to latch off after an overload then you need to add a latch.

Note that an N-MOSFET is acting as a source-follower to limit the current, which means the output will never be higher than the MOSFET Vgs(th) below the input.
If you want the output voltage to be equal to the input, a P-MOSFET should be used.
That will reverse the polarity of the current limit signal.

Click to expand...

Changed it to a PMOS with a discrete NMOS inverter to invert comp output to correct level - much better, it reclaims about 2.5V headroom compared to the NMOS so great, thanks, super suggestion.

- - - Updated - - -

dick_freebird said:

If you want latched overcurrent protection then there
had better be a latch (SRFF) in the lineup somewhere.
I see none, so the mode is probably comparator chatter
(motorboating, similar to UVLO behaviors) which after
the filter looks like something continuous.

Which the user prefers, is a question. Needing to power-
cycle after every momentary current spike is not well
received in some circles.

Click to expand...

Hi,

Yes, I agree in some ways, whenever I read about power cycling it conjures up images of some poor tech guy who has to drives hundreds of miles to some bleak, windswept, rainy place just to flick a trip switch every few days.

In this case, the user loves the idea. It's a(nother) torch I'll be using. Besides my unhealthy compulsion for torch circuits, as the end user I want it to go off if a string blows to alert me to the problem - let's hope it doesn't happen in the dark. Hiccup mode related to lighting devices is just annoying, frankly.

I am going to second the observation that others have posted:
If you plan to use a latching function, you better have a robust qualifier for the overcurrent condition.
Otherwise nuisance tripping will drive you crazy.
The qualifier may be some sort of I2t function, wheread the latching response is a function of the overcurrent level.

Latching also makes the case for having some limited amount of restart attempts, each restart separated by a period of time. After which it will permanently latch off.

Of course, to properly implement such algorithm would require a microcontroller. But a tiny 6 pin device could be sufficient. It may end being simpler and cheaper than a hardware solution.

Hi,

What do you mean by robust qualifier, please? The same as FvM said about a time filter? I2t = time filter?

Last night I tinkered with the simulation adding a capacitor to the MOSFET gate and a couple of other places, and got the inrush spike down from ~1.5V (bad) to about 1.1V (good) but occasionally those circuit versions gave erratic simulation results/results with bad news somewhere or other (read the numbers and weep and tweak again...).

Provisional latching attempts with a monostable 555 and then a monostable 555 controlled by an astable 555 controlled by its reset pin didn't work as intended and I haven't got any flip flops. For a crummy and ideally compact and slimline torch I really wonder if it's worth this much PBC space for what the torch needs to do. An SMD fuse would solve the problem quickly, too when seen from a practical design viewpoint. I saw an advert for a load switch the other day and think that would be the most sensible option along with a timeout but I see your point about the uC - one day I may dare to try learning to wrestle with one.

"Latching also makes the case for having some limited amount of restart attempts, each restart separated by a period of time. After which it will permanently latch off." - That's a really good idea for a failsafe approach to avoid false triggering which I would never have thought of, thanks.

Yes, that is what I meant.
I squared t means that if your current overload doubles, then the reaction time has to be cut by one quarter.

Do you have any NAND or NOR CMOS gates lying around? You can make simple SR latches by cross-feeding a pair of gates. Google it.