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    Fractional Frequency divider using Sigma Delta Modulator

    Hello everyone,
    i am working on sigma delta modulator that I need to use in the fractional divider. Like for now I am facing the noise shaping phenomena and I do not understand one thing... Let me describe the problem:

    I know why the noise shaping occurs in sigma delta and can see it in the simulation of 2 nd order sigma delta (verilog model). I am applying 1 kHz sine wave at modulator input and using sampling clock of 1Meg. The noise shaping is present around the frequency of 1kHz, at modulator output hovewer when I use this modulator to control the divider (changing the dividing factor) I can't see the noise shaping around the output signal of divider. For instance I have 10Meg divider input, I am dividing it by 7 or 8 depending on sigma delta output - 0 or 1 and I can't see the noise shaping around 1.4 Meg that I have got at divider output. What I expect is that I will have the same noise shaping around the output fequency as I got around sigma delta output.
    My question is...should I expect the noise shaping around output of divider ? How does the sigma delta controling cause the noise around the divider output to be shaped ? I know why I see it at the modulator outptut but I am not sure why should I see it at the divider output also.

    Modulator output:
    Click image for larger version. 

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    Divider output(i do not why I the output frequency look like this - there is a lot of distortions near the output frequency):
    Click image for larger version. 

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    I do not now whether I have presented it clearly...In case of question please ask.
    I will provide more data like schematic, simulation results if needed.

    Thanks & Regards,
    jack

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    Re: Fractional Frequency divider using Sigma Delta Modulator

    Quote Originally Posted by jackeeer View Post
    My question is...should I expect the noise shaping around output of divider ?
    Yes.

    Quote Originally Posted by jackeeer View Post
    How does the sigma delta controling cause the noise around the divider output to be shaped ?
    I know why I see it at the modulator outptut
    but I am not sure why should I see it at the divider output also.
    Strictly speaking, Noise shaping affects phase not voltage of output signal.

    Phase is shaped as lowpass type noise shaping.
    And voltage is shaped as bandpass type noise shaping, as far as phase deviation is small.

    Zoom around 1.4MHz.
    You can see bandpass noise shaping.

    Also see the followings.
    http://www.designers-guide.org/Forum...1444923186/6#6
    http://www.designers-guide.org/Forum...1361756819/3#3

    You have to understand that noise shaping order of phase reduces by one.
    For order_3,
    Modualtor have gradient of 60dB/dec.
    Phase of divider have gradient of 40dB/dec.
    Last edited by pancho_hideboo; 13th May 2018 at 06:07.



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    Re: Fractional Frequency divider using Sigma Delta Modulator

    Thanks for your reply pancho_hideboo,

    Can you point the place where you see the noise shaping at my printscreen of freq divider output?
    I understand the noise may be shaped not so efficient like at the modulator output but I have expected it
    shape will be similar. I found some publicaton regarding fractional freq divider that uses sigma delta to
    control the div factor and the output spectrum there was as follows:
    Click image for larger version. 

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    1:Why do not I see similar thing?
    2:Why can't I see single product at the output frequncy? - there are many product near the output that have
    comparable magnitude.


    I will read more about phase noise shaping...

    Thanks one more time,
    jackeeer
    Last edited by jackeeer; 13th May 2018 at 11:27.



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    Re: Fractional Frequency divider using Sigma Delta Modulator

    Quote Originally Posted by jackeeer View Post
    Can you point the place where you see the noise shaping at my printscreen of freq divider output?
    Surely read my append in https://www.edaboard.com/showthread....ta-Modulator#2.

    Quote Originally Posted by jackeeer View Post
    I understand the noise may be shaped not so efficient like at the modulator output
    No.
    You can not understand anything at all.

    Quote Originally Posted by jackeeer View Post
    1:Why do not I see similar thing?
    2:Why can't I see single product at the output frequncy? - there are many product near the output that have comparable magnitude.
    Surely consider bandwidth of spectrum.
    Your lowpass noise shaping is 50kHz bandwidth.

    And surely understand PLL.
    Your spectrum is not PLL.

    And your divide-ratio is very small.
    This results in large phase deviation.
    So small angular approximation can not be satisfied.
    Last edited by pancho_hideboo; 13th May 2018 at 12:28.


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    Re: Fractional Frequency divider using Sigma Delta Modulator

    Thanks for help. I did another simulation for 10 ms, fin 100 Mhz, div by 3 or 4. I have got following results:

    Click image for larger version. 

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    Click image for larger version. 

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    Has anybody know why cant I see the peak at frequency (100MHz/3.5 (3.5 is div factor) ) and the noise shaping?


    Regards,
    jackeeer

    - - - Updated - - -

    One more question: Does my Noise Shaping bandwidth (thats 50KHz) need to be in some relation with the output frequency of divider?

    Regards,
    jackeeer



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    Re: Fractional Frequency divider using Sigma Delta Modulator

    Quote Originally Posted by jackeeer View Post
    I did another simulation for 10 ms,
    delta_f=0.1kHz.

    Quote Originally Posted by jackeeer View Post
    fin 100 Mhz, div by 3 or 4.
    Has anybody know why cant I see the peak at frequency (100MHz/3.5 (3.5 is div factor) )
    Divide ratio is too small.

    Ntotal=N + delta_N=N*(1+delta_N/N), N=3, delta_N=0 or 1
    Max(delta_N/N)=1/3=0.3333 is too large

    fout = fin/Ntot

    Quote Originally Posted by jackeeer View Post
    and the noise shaping?
    I can not understand what you want to mean at all.

    Quote Originally Posted by jackeeer View Post
    One more question: Does my Noise Shaping bandwidth (thats 50KHz) need to be in some relation with the output frequency of divider?
    Surey learn very basic things.
    Simply clock of your Delta-Sigma-Modulator is 50kHz, that's all.
    Last edited by pancho_hideboo; 15th May 2018 at 12:33.



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    Re: Fractional Frequency divider using Sigma Delta Modulator

    Can you please tell why I need to increase it instead of saying I need to do it?
    For higher dividing ratio the output has too low frequency in compare to sigma delta output - this is why I did not want to do this. Moreover for lower div ratio I need to make my simulating longer...

    I can increase the divider ratio let's say 31.5 but what I should do in case I want see the noise shaping for dividing ratio of 3.5 ? Assiming I can't increase the divider ratio...what should I change to see noise shaped?

    Regards,
    jackeeer



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    Re: Fractional Frequency divider using Sigma Delta Modulator

    Can you understand Phase Modulation and small angular approximation ?
    If not, learn very basic things.

    BTW, what frequency do you use as clock of divider ?

    For small divide ratio such as 3.5, DSM PLL can not work.

    See PLL products of ADI, TI, etc.



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    Re: Fractional Frequency divider using Sigma Delta Modulator

    I meant "Moreover for HIGHER div ratio I need to make my simulating longer..."

    YES, I am familiar with those two concepts however it is first time I do something with sigma-delta modulator and factioanal dividing.

    So far I have used 10 MHz and 100 MHz as divider clock input and mostly 20 KHz of SD samppling clock .

    "For small divide ratio such as 3.5, DSM PLL can not work." - will not work at all, by definiton? or I need to change something to make it work ?
    It is only verilog model based sigma delta and Dual Modulus Divider - i should see somehow the noise shapping at the output but I suppose my sigma delta samppling frequency is in wrong relation to input of frequency divider or something...

    I will not use it in PLL - I am working only on Fractional Divider.

    Regards,
    jackeeer
    Last edited by jackeeer; 15th May 2018 at 19:21.



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    Re: Fractional Frequency divider using Sigma Delta Modulator

    Quote Originally Posted by jackeeer View Post
    I know why the noise shaping occurs in sigma delta
    and can see it in the simulation of 2 nd order sigma delta (verilog model).
    ...........................................
    For instance I have 10Meg divider input,
    I am dividing it by 7 or 8 depending on sigma delta output - 0 or 1
    Can you surely understand very basics of DSM(Delta Sigma Modulator) ?

    Instantaneous divide-ratio is Ninst = N + delta_N.

    For first order Delta Sigma Modulator generates {0, 1} as delta_N.
    N must be far larger than two.

    For second order Delta Sigma Modulator generates {-1, 0, 1, 2} as delta_N.
    N must be far larger than three.

    For third order Delta Sigma Modulator generates {-3, -2, -1, 0, 1, 2, 3, 4} as delta_N.
    N must be far larger than five.

    So if order of your DSM is truely second, your descriptions are wrong completely.

    Is order of your DSM first, isn't it ?

    Quote Originally Posted by jackeeer View Post
    YES, I am familiar with those two concepts
    No.
    You can not understand even very basic things at all.
    If you can truely understand Phase Modulation and small angular approximation, answers are self-evident.

    Nints = N + delta_N = N * (1 + delta_N/N)

    Tout = Tin * Ninst
    fout = fin / Ninst

    Output of divider is none of them.

    For simplicity, I use sinusoidal.
    Vout = A * sin(phase_out)
    phase_out = phase_in / Ninst.

    Output of divider is Vout.

    If delta_N/N is small, sidebands of Vout are far apart.

    Moreover output of divider is not sinusoidal.

    Quote Originally Posted by jackeeer View Post
    "For small divide ratio such as 3.5, DSM PLL can not work." - will not work at all, by definiton?
    By definition.


    Quote Originally Posted by jackeeer View Post
    It is only verilog model based sigma delta and Dual Modulus Divider
    - i should see somehow the noise shapping at the output
    but I suppose my sigma delta samppling frequency is in wrong relation to input of frequency divider or something...
    Completely wrong.
    Can you surely understand very basics of Sampling theory ?
    There is no direct relation between sampling frequency of DSM and input frequency of divider.

    Generally, output signal of divider is used as sampling clock of DSM.

    However high sampling clock is preferable due to oversampling effect.
    High sampling clock than input frequency of divider is nonsense.

    Quote Originally Posted by jackeeer View Post
    So far I have used 10 MHz and 100 MHz as divider clock input
    and mostly 20 KHz of SD samppling clock.
    I don't think your sampling clock is 20kHz.
    Judging from https://www.edaboard.com/attachment....5&d=1526336635 is 40kHz.
    Last edited by pancho_hideboo; 16th May 2018 at 12:30.



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    Re: Fractional Frequency divider using Sigma Delta Modulator

    Thanks for your reply pancho_hideboo,

    It seems I need to read more about SD modulators. I thought my dividing ratio will be purely N or N+1 depending on sigma delta output signal - high or low.

    I am using following verilog-A code for 2nd order SD modulator. Please look.

    Code Verilog - [expand]
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    analog begin
     
          @ ( initial_step ) begin
             vout_val = 1.0;
             hi=1.0;
             lo=-1.0;
          end
     
          @ (cross(V(vclk), 0))begin
     
             // summing junction
             vsum = V(vin) - vd ;
             
             // integrator
             vint = vsum + vint;
             // summing junction
             vsum2 = vint - vd ;
             
             // integrator
             vint2 = vsum2 + vint2;
             // quantizer
             if (vint2 > vth)
                vout_val = hi ;
         else
                vout_val = lo ;
             
             // D2A
             vd = vout_high * vout_val ;
             
          end
          V(vout) <+ transition(vout_val, tdel, trise, tfall);
       end
    endmodule

    (is there some "code" section I can put it to??? :) )
    And also the tbs:

    Click image for larger version. 

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ID:	146674


    Regards,
    jackeeer



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    Re: Fractional Frequency divider using Sigma Delta Modulator

    Surely learn very basics before posting.

    Quote Originally Posted by jackeeer View Post
    It seems I need to read more about SD modulators.
    Simply you can not understand even very basic things at all.

    Quote Originally Posted by jackeeer View Post
    I am using following verilog-A code for 2nd order SD modulator.
    Completely wrong.
    This is second order DSM ADC of 1bit.

    Surely learn very basics before posting.

    Even if you use correct DSM, you have to increase divide-ratio.

    Surely learn very basics before posting.
    Last edited by pancho_hideboo; 16th May 2018 at 17:40.



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    Re: Fractional Frequency divider using Sigma Delta Modulator

    Yes, this is 1 bit output SDM. I use it to investigate on SDM working and noise shaping. As I posted at the begining of this thread I see the noise shaping at the SDM output. I've thought I can use it to control Dual Modulus Divider (n or n+1) and would see the noise shaping...Is there a chance I will see the noise shaping using 1 bit modulator to control DMD?

    As I said all above was simulated using verilog-A model however I am designing the secon order SDM using swich capacitor signal integrators, comparators, 1 bit DAC. I see the noise shaping using my transistor based SDM circuit. Why can't I see it using verilog-A model?

    Can you please stop saying "Surely learn very basics before posting."? It came to me when you said it in second post. :) I know I need to learn much. I am starting working on SDM and do not understand some concepts but also there is many missunderstandings in our conversation.

    Thanks & Regards,
    jackeeer



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    Re: Fractional Frequency divider using Sigma Delta Modulator

    Quote Originally Posted by jackeeer View Post
    Is there a chance I will see the noise shaping using 1 bit modulator to control DMD?
    Possible for fisrt order DSM.

    Quote Originally Posted by jackeeer View Post
    I am designing the secon order SDM using swich capacitor signal integrators, comparators, 1 bit DAC.
    I see the noise shaping using my transistor based SDM circuit.
    Surely see results.
    Results must be absolutely wrong.

    Simply you can not understand range-scaling and overflow of integrator of DSM.

    Quote Originally Posted by jackeeer View Post
    Why can't I see it using verilog-A model?
    Simply lack of your ability.
    Again see http://www.designers-guide.org/Forum...1361756819/3#3
    http://www.designers-guide.org/Forum...s/hoge_001.jpg
    I also use DSM of Verilog-A.

    I don't know what simulator you use.
    However If you use Cadence dfII, you can find samples in $CDS_TOP_DIR/IC/tools/dfII/samples/artist/pllMMLib.

    BTW, I don't use them since I can write more good models by myself

    Quote Originally Posted by jackeeer View Post
    I am starting working on SDM and do not understand some concepts
    What you can not understand is not only DSM.

    Surely learn very basics before posting.
    Last edited by pancho_hideboo; 16th May 2018 at 18:52.



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    Re: Fractional Frequency divider using Sigma Delta Modulator

    Thank you for your honesty.
    Correct me if I am wrong:
    Does your explanation correspond to MASH type of Sigma Delta ?

    If I understand you I can use only 1st order sigma delta for Dual Modulus Divider...For higher orders I need to use MULTI modulus divider that has multi bits control signal....But what when my Second order sigma delta has one bit output like in this case? Is it also unusable to see noise shaping ?

    Thanks,
    jackeeer



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    Re: Fractional Frequency divider using Sigma Delta Modulator

    Quote Originally Posted by jackeeer View Post
    Does your explanation correspond to MASH type of Sigma Delta ?
    No.
    It is true for any DSM structures such as CIFF, CIFB, and MASH.
    Attached figure show MASH and CIFF.

    Quote Originally Posted by jackeeer View Post
    If I understand you I can use only 1st order sigma delta for Dual Modulus Divider...
    Correct.

    Quote Originally Posted by jackeeer View Post
    For higher orders I need to use MULTI modulus divider that has multi bits control signal...
    Correct.

    Quote Originally Posted by jackeeer View Post
    But what when my Second order sigma delta has one bit output like in this case?
    You can not control frequency divider as target fractional divide-ratio.

    Quote Originally Posted by jackeeer View Post
    Is it also unusable to see noise shaping ?
    Simply you can not understand anything.

    Noise Shaping and averaging as fractional value are different.

    Surely learn range-scaling and overflow of DSM.
    Last edited by pancho_hideboo; 16th May 2018 at 20:39.



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    Re: Fractional Frequency divider using Sigma Delta Modulator

    Ok, so from your explanation the second order sigma delta (used in fractional divider) should have 2 bits output that will change between following states :{-1, 0, 1, 2} but there is a lot of examples of 2nd order sigma delta that has 1 bit output. SO What are they use for? Are they used only for ADC/DAC conversion ?

    Regards,
    jackeeer



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    Re: Fractional Frequency divider using Sigma Delta Modulator

    Quote Originally Posted by jackeeer View Post
    but there is a lot of examples of 2nd order sigma delta that has 1 bit output.
    SO What are they use for?
    Are they used only for ADC/DAC conversion ?
    Yes.

    Surely learn and study range scaling of DSM.


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