Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

CMOS 0.18um 100 dB DC gain 1GHz UGB and rail-to-rail input stage opamp design

Status
Not open for further replies.
azizbaskan

azizbaskan

Newbie
Joined
May 12, 2018
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
185
Hi everyone. I am designing a high gain high bandwidth opamp with rail to rail input stage in 0.18um CMOS technology. Power supply is 3.3V.

I need advice from experienced designers. Which architecture should I use or which papers should I refer to ?
I already made a research about rail to rail input stage and found that a constant gm input stage and a folded cascode structure is used generally. Is it possible to reach 100 dB DC gain without gain boosting or do I need to use folded cascode structure with gain boosting ?. Also, is it possible to have 1GHz unity gain bandwidth and 100 dB DC gain with this technology?

Thanks in advance.
 

I think it is not possible. The DC gain is reachable with cascodes but the 1GHz UGBW is extreme high. If you really want an OPAmp I assume you want feedback, and if somehow with large currents you can set the dominant pole to 1GHz I am almost sure you cannot place the 2nd lowest pole to much higher frequency. It will oscillate, without load and layout parasitics. Especially at 3.3V where the devices are bigger than 1.8V core transistors. With 1.8V devices possible to create an amplifier at 1GHz, but with BPF characteristic.
Probably gain boosting won't increase the bandwidth, I don't have experience with that.
 
what's the value of your loading capacitor? I think there is chance to get your goal with telescope amplifier structure and gain boosting technique under the 3.3V supply. however, you have to take the robust into your consideration with the 3.3V supply voltage.
 

So, you need more than 63mS of transconductance and at least 10GHz of transit frequency in all mosfets to achieve 1GHz UGF with 45° phase margin (and it would be an upper limit). The 180nm process provide core devices with f_t ≈60GHz, you would like to use 3.3V so I/O mosfets, which probably has Lmin 500nm and f_t in order of 5GHz. Then, forget with any known single stage architecture. You could consider using a core devices with 3.3V, however they has to be ensured to safe operation (all SOA, reliability checks, etc).
 

azizbaskan said:
Hi everyone. I am designing a high gain high bandwidth opamp with rail to rail input stage in 0.18um CMOS technology. Power supply is 3.3V.

I need advice from experienced designers. Which architecture should I use or which papers should I refer to ?
I already made a research about rail to rail input stage and found that a constant gm input stage and a folded cascode structure is used generally. Is it possible to reach 100 dB DC gain without gain boosting or do I need to use folded cascode structure with gain boosting ?. Also, is it possible to have 1GHz unity gain bandwidth and 100 dB DC gain with this technology?

Thanks in advance.
Click to expand...

I assume that the structure you have researched is a complementary CMOS input pair (using both PMOS and NMOS to achieve rail-to-rail input). This is unrelated to your requirements of gain and UGBW. But I would like to point out that, depending on your application, the structure has an very poor common-mode rejection. This is a result of mismatch between the offset of NMOSs and PMOSs pair. If you care about signal distortion, you have to consider this fact.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top